| Message ID | 20250223122227.725233-4-ivo.ivanov.ivanov1@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | phy: samsung: add Exynos2200 SNPS eUSB2 driver | expand |
On Sun, 23 Feb 2025 14:22:22 +0200, Ivaylo Ivanov wrote: > The Exynos2200 SoC has a USB controller PHY, which acts as an > intermediary between a USB controller (typically DWC3) and other PHYs > (UTMI, PIPE3). Add a dt-binding schema for it. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > .../phy/samsung,exynos2200-usbcon-phy.yaml | 76 +++++++++++++++++++ > 1 file changed, 76 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.example.dts:18:18: fatal error: dt-bindings/clock/samsung,exynos2200-cmu.h: No such file or directory 18 | #include <dt-bindings/clock/samsung,exynos2200-cmu.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1511: dt_binding_check] Error 2 make: *** [Makefile:251: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250223122227.725233-4-ivo.ivanov.ivanov1@gmail.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml new file mode 100644 index 000000000..7d879ec8b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos2200-usbcon-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Exynos2200 USB controller PHY + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + +description: + Exynos2200 USB controller PHY is an intermediary between a USB controller + (typically DWC3) and other PHYs (UTMI, PIPE3). + +properties: + compatible: + enum: + - samsung,exynos2200-usbcon-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: bus clock + + clock-names: + items: + - const: bus + + "#phy-cells": + const: 0 + + phys: + maxItems: 1 + description: + Phandle to eUSB2 PHY + + samsung,pmu-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + minItems: 1 + items: + - description: phandle for PMU system controller interface, used to + control PMU registers bits for USBCON PHY + - description: offset of the pmu control register + description: + Should be phandle/offset pair. The phandle to System Register syscon node + and the offset for USBCON PHY. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - phys + - samsung,pmu-syscon + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos2200-cmu.h> + + usb_con_phy: phy@10aa0000 { + compatible = "samsung,exynos2200-usbcon-phy"; + reg = <0x10aa0000 0x10000>; + clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; + clock-names = "bus"; + #phy-cells = <0>; + phys = <&usb_hs_phy>; + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; + };
The Exynos2200 SoC has a USB controller PHY, which acts as an intermediary between a USB controller (typically DWC3) and other PHYs (UTMI, PIPE3). Add a dt-binding schema for it. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- .../phy/samsung,exynos2200-usbcon-phy.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml