diff mbox series

[4/5] drm/mediatek: Add MDP-RSZ component support for MT8196

Message ID 20250211025317.399534-5-sunny.shen@mediatek.com (mailing list archive)
State New
Headers show
Series Add components to support PQ in display path for MT8196 | expand

Commit Message

Sunny Shen (沈姍姍) Feb. 11, 2025, 2:52 a.m. UTC 
Add MDP-RSZ component support for MT8196.

Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
 3 files changed, 27 insertions(+)

Comments

CK Hu (胡俊光) Feb. 17, 2025, 6:04 a.m. UTC | #1 
On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Add MDP-RSZ component support for MT8196.
> 
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> index 7f09a8977965..65878d3fe8a9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> @@ -46,6 +46,10 @@
>  #define DSC_BYPASS				BIT(4)
>  #define DSC_UFOE_SEL				BIT(16)
>  
> +#define DISP_REG_MDP_RSZ_EN			0x0000

Do you config resizer in bypass mode so you need not to enable it?

> +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> +
>  #define DISP_REG_OD_EN				0x0000
>  #define DISP_REG_OD_CFG				0x0020
>  #define OD_RELAYMODE				BIT(0)
> @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
>  	writel(1, priv->regs + DISP_REG_OD_EN);
>  }
>  
> +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> +			       unsigned int h, unsigned int vrefresh,
> +			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);

Do you config resizer in bypass mode so width and height is set to zero?

Regards,
CK

> +}
> +
>  static void mtk_postmask_config(struct device *dev, unsigned int w,
>  				unsigned int h, unsigned int vrefresh,
>  				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
>  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> +	.clk_enable = mtk_ddp_clk_enable,
> +	.clk_disable = mtk_ddp_clk_disable,
> +	.config = mtk_mdp_rsz_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_postmask = {
>  	.clk_enable = mtk_ddp_clk_enable,
>  	.clk_disable = mtk_ddp_clk_disable,
> @@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>  	[MTK_DISP_DITHER] = "dither",
>  	[MTK_DISP_DSC] = "dsc",
>  	[MTK_DISP_GAMMA] = "gamma",
> +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
>  	[MTK_DISP_MERGE] = "merge",
>  	[MTK_DISP_MUTEX] = "mutex",
>  	[MTK_DISP_OD] = "od",
> @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
>  	[DDP_COMPONENT_DSI2]		= { MTK_DSI,			2, &ddp_dsi },
>  	[DDP_COMPONENT_DSI3]		= { MTK_DSI,			3, &ddp_dsi },
>  	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,		0, &ddp_gamma },
> +	[DDP_COMPONENT_MDP_RSZ0]	= { MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
>  	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,		0, &ddp_merge },
>  	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,		1, &ddp_merge },
>  	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,		2, &ddp_merge },
> diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> index badb42bd4f7c..87f573fcc903 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
>  	MTK_DISP_OVLSYS_ADAPTOR,
>  	MTK_DISP_OVL_2L,
>  	MTK_DISP_OVL_ADAPTOR,
> +	MTK_DISP_MDP_RSZ,
>  	MTK_DISP_POSTMASK,
>  	MTK_DISP_PWM,
>  	MTK_DISP_RDMA,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 50f5f81a7da1..b810a197f58b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>  	  .data = (void *)MTK_DISP_GAMMA, },
>  	{ .compatible = "mediatek,mt8195-disp-gamma",
>  	  .data = (void *)MTK_DISP_GAMMA, },
> +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> +	  .data = (void *)MTK_DISP_MDP_RSZ },
>  	{ .compatible = "mediatek,mt8195-disp-merge",
>  	  .data = (void *)MTK_DISP_MERGE },
>  	{ .compatible = "mediatek,mt2701-disp-mutex",
Sunny Shen (沈姍姍) Feb. 23, 2025, 5:52 p.m. UTC | #2 
On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote:
> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > Add MDP-RSZ component support for MT8196.
> > 
> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
> >  3 files changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > index 7f09a8977965..65878d3fe8a9 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > @@ -46,6 +46,10 @@
> >  #define DSC_BYPASS				BIT(4)
> >  #define DSC_UFOE_SEL				BIT(16)
> >  
> > +#define DISP_REG_MDP_RSZ_EN			0x0000
> 
> Do you config resizer in bypass mode so you need not to enable it?

Yes, it's bypass mode
To use the hardware path for PQ,
we need set this resizer to bypass mode because the path mux design of
the MT8196

> 
> > +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> > +
> >  #define DISP_REG_OD_EN				0x0000
> >  #define DISP_REG_OD_CFG				0x0020
> >  #define OD_RELAYMODE				BIT(0)
> > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
> >  	writel(1, priv->regs + DISP_REG_OD_EN);
> >  }
> >  
> > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> > +			       unsigned int h, unsigned int
> > vrefresh,
> > +			       unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
> 
> Do you config resizer in bypass mode so width and height is set to
> zero?

Yes, we set resizer's width and height to 0 and use the bypass mode

> 
> Regards,
> CK
> 
> > +}
> > +
> >  static void mtk_postmask_config(struct device *dev, unsigned int
> > w,
> >  				unsigned int h, unsigned int
> > vrefresh,
> >  				unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ovlsys_adaptor = {
> >  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
> >  };
> >  
> > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> > +	.clk_enable = mtk_ddp_clk_enable,
> > +	.clk_disable = mtk_ddp_clk_disable,
> > +	.config = mtk_mdp_rsz_config,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_postmask = {
> >  	.clk_enable = mtk_ddp_clk_enable,
> >  	.clk_disable = mtk_ddp_clk_disable,
> > @@ -454,6 +476,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >  	[MTK_DISP_DITHER] = "dither",
> >  	[MTK_DISP_DSC] = "dsc",
> >  	[MTK_DISP_GAMMA] = "gamma",
> > +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
> >  	[MTK_DISP_MERGE] = "merge",
> >  	[MTK_DISP_MUTEX] = "mutex",
> >  	[MTK_DISP_OD] = "od",
> > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
> >  	[DDP_COMPONENT_DSI2]		= {
> > MTK_DSI,			2, &ddp_dsi },
> >  	[DDP_COMPONENT_DSI3]		= {
> > MTK_DSI,			3, &ddp_dsi },
> >  	[DDP_COMPONENT_GAMMA]		= {
> > MTK_DISP_GAMMA,		0, &ddp_gamma },
> > +	[DDP_COMPONENT_MDP_RSZ0]	= {
> > MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
> >  	[DDP_COMPONENT_MERGE0]		= {
> > MTK_DISP_MERGE,		0, &ddp_merge },
> >  	[DDP_COMPONENT_MERGE1]		= {
> > MTK_DISP_MERGE,		1, &ddp_merge },
> >  	[DDP_COMPONENT_MERGE2]		= {
> > MTK_DISP_MERGE,		2, &ddp_merge },
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > index badb42bd4f7c..87f573fcc903 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> >  	MTK_DISP_OVLSYS_ADAPTOR,
> >  	MTK_DISP_OVL_2L,
> >  	MTK_DISP_OVL_ADAPTOR,
> > +	MTK_DISP_MDP_RSZ,
> >  	MTK_DISP_POSTMASK,
> >  	MTK_DISP_PWM,
> >  	MTK_DISP_RDMA,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 50f5f81a7da1..b810a197f58b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -885,6 +885,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >  	  .data = (void *)MTK_DISP_GAMMA, },
> >  	{ .compatible = "mediatek,mt8195-disp-gamma",
> >  	  .data = (void *)MTK_DISP_GAMMA, },
> > +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> > +	  .data = (void *)MTK_DISP_MDP_RSZ },
> >  	{ .compatible = "mediatek,mt8195-disp-merge",
> >  	  .data = (void *)MTK_DISP_MERGE },
> >  	{ .compatible = "mediatek,mt2701-disp-mutex",
>
CK Hu (胡俊光) Feb. 24, 2025, 2:07 a.m. UTC | #3 
On Sun, 2025-02-23 at 17:52 +0000, Sunny Shen (沈姍姍) wrote:
> On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote:
> > On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > > Add MDP-RSZ component support for MT8196.
> > > 
> > > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24
> > > ++++++++++++++++++++++++
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +
> > >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
> > >  3 files changed, 27 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > index 7f09a8977965..65878d3fe8a9 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
> > > @@ -46,6 +46,10 @@
> > >  #define DSC_BYPASS				BIT(4)
> > >  #define DSC_UFOE_SEL				BIT(16)
> > >  
> > > +#define DISP_REG_MDP_RSZ_EN			0x0000
> > 
> > Do you config resizer in bypass mode so you need not to enable it?
> 
> Yes, it's bypass mode
> To use the hardware path for PQ,
> we need set this resizer to bypass mode because the path mux design of
> the MT8196
> 
> > 
> > > +#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
> > > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
> > > +
> > >  #define DISP_REG_OD_EN				0x0000
> > >  #define DISP_REG_OD_CFG				0x0020
> > >  #define OD_RELAYMODE				BIT(0)
> > > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)
> > >  	writel(1, priv->regs + DISP_REG_OD_EN);
> > >  }
> > >  
> > > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
> > > +			       unsigned int h, unsigned int
> > > vrefresh,
> > > +			       unsigned int bpc, struct cmdq_pkt
> > > *cmdq_pkt)
> > > +{
> > > +	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > +
> > > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > > +		      DISP_REG_MDP_RSZ_INPUT_SIZE);
> > > +	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > > +		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
> > 
> > Do you config resizer in bypass mode so width and height is set to
> > zero?
> 
> Yes, we set resizer's width and height to 0 and use the bypass mode

Add comment for this so others would know why not enable it and why set width/height to zero.

Regards,
CK

> 
> > 
> > Regards,
> > CK
> > 
> > > +}
> > > +
> > >  static void mtk_postmask_config(struct device *dev, unsigned int
> > > w,
> > >  				unsigned int h, unsigned int
> > > vrefresh,
> > >  				unsigned int bpc, struct cmdq_pkt
> > > *cmdq_pkt)
> > > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs
> > > ddp_ovlsys_adaptor = {
> > >  	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
> > >  };
> > >  
> > > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
> > > +	.clk_enable = mtk_ddp_clk_enable,
> > > +	.clk_disable = mtk_ddp_clk_disable,
> > > +	.config = mtk_mdp_rsz_config,
> > > +};
> > > +
> > >  static const struct mtk_ddp_comp_funcs ddp_postmask = {
> > >  	.clk_enable = mtk_ddp_clk_enable,
> > >  	.clk_disable = mtk_ddp_clk_disable,
> > > @@ -454,6 +476,7 @@ static const char * const
> > > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > >  	[MTK_DISP_DITHER] = "dither",
> > >  	[MTK_DISP_DSC] = "dsc",
> > >  	[MTK_DISP_GAMMA] = "gamma",
> > > +	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
> > >  	[MTK_DISP_MERGE] = "merge",
> > >  	[MTK_DISP_MUTEX] = "mutex",
> > >  	[MTK_DISP_OD] = "od",
> > > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match
> > > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
> > >  	[DDP_COMPONENT_DSI2]		= {
> > > MTK_DSI,			2, &ddp_dsi },
> > >  	[DDP_COMPONENT_DSI3]		= {
> > > MTK_DSI,			3, &ddp_dsi },
> > >  	[DDP_COMPONENT_GAMMA]		= {
> > > MTK_DISP_GAMMA,		0, &ddp_gamma },
> > > +	[DDP_COMPONENT_MDP_RSZ0]	= {
> > > MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
> > >  	[DDP_COMPONENT_MERGE0]		= {
> > > MTK_DISP_MERGE,		0, &ddp_merge },
> > >  	[DDP_COMPONENT_MERGE1]		= {
> > > MTK_DISP_MERGE,		1, &ddp_merge },
> > >  	[DDP_COMPONENT_MERGE2]		= {
> > > MTK_DISP_MERGE,		2, &ddp_merge },
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > index badb42bd4f7c..87f573fcc903 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
> > > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> > >  	MTK_DISP_OVLSYS_ADAPTOR,
> > >  	MTK_DISP_OVL_2L,
> > >  	MTK_DISP_OVL_ADAPTOR,
> > > +	MTK_DISP_MDP_RSZ,
> > >  	MTK_DISP_POSTMASK,
> > >  	MTK_DISP_PWM,
> > >  	MTK_DISP_RDMA,
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > index 50f5f81a7da1..b810a197f58b 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > @@ -885,6 +885,8 @@ static const struct of_device_id
> > > mtk_ddp_comp_dt_ids[] = {
> > >  	  .data = (void *)MTK_DISP_GAMMA, },
> > >  	{ .compatible = "mediatek,mt8195-disp-gamma",
> > >  	  .data = (void *)MTK_DISP_GAMMA, },
> > > +	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
> > > +	  .data = (void *)MTK_DISP_MDP_RSZ },
> > >  	{ .compatible = "mediatek,mt8195-disp-merge",
> > >  	  .data = (void *)MTK_DISP_MERGE },
> > >  	{ .compatible = "mediatek,mt2701-disp-mutex",
> > 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 7f09a8977965..65878d3fe8a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -46,6 +46,10 @@ 
 #define DSC_BYPASS				BIT(4)
 #define DSC_UFOE_SEL				BIT(16)
 
+#define DISP_REG_MDP_RSZ_EN			0x0000
+#define DISP_REG_MDP_RSZ_INPUT_SIZE		0x0010
+#define DISP_REG_MDP_RSZ_OUTPUT_SIZE		0x0014
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -235,6 +239,18 @@  static void mtk_od_start(struct device *dev)
 	writel(1, priv->regs + DISP_REG_OD_EN);
 }
 
+static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,
+			       unsigned int h, unsigned int vrefresh,
+			       unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MDP_RSZ_INPUT_SIZE);
+	mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MDP_RSZ_OUTPUT_SIZE);
+}
+
 static void mtk_postmask_config(struct device *dev, unsigned int w,
 				unsigned int h, unsigned int vrefresh,
 				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -391,6 +407,12 @@  static const struct mtk_ddp_comp_funcs ddp_ovlsys_adaptor = {
 	.get_num_formats = mtk_ovlsys_adaptor_get_num_formats,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_mdp_rsz_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_postmask = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -454,6 +476,7 @@  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MDP_RSZ] = "mdp-rsz",
 	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -515,6 +538,7 @@  static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,			2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,			3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,		0, &ddp_gamma },
+	[DDP_COMPONENT_MDP_RSZ0]	= { MTK_DISP_MDP_RSZ,		0, &ddp_mdp_rsz},
 	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,		0, &ddp_merge },
 	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,		1, &ddp_merge },
 	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,		2, &ddp_merge },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index badb42bd4f7c..87f573fcc903 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -36,6 +36,7 @@  enum mtk_ddp_comp_type {
 	MTK_DISP_OVLSYS_ADAPTOR,
 	MTK_DISP_OVL_2L,
 	MTK_DISP_OVL_ADAPTOR,
+	MTK_DISP_MDP_RSZ,
 	MTK_DISP_POSTMASK,
 	MTK_DISP_PWM,
 	MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 50f5f81a7da1..b810a197f58b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -885,6 +885,8 @@  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8195-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8196-disp-mdp-rsz",
+	  .data = (void *)MTK_DISP_MDP_RSZ },
 	{ .compatible = "mediatek,mt8195-disp-merge",
 	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",