| Message ID | 20250224074928.2005744-1-kever.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v6,1/2] dt-bindings: PCI: dw: rockchip: Add rk3576 support | expand |
On Mon, Feb 24, 2025 at 03:49:27PM +0800, Kever Yang wrote: > rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC > instead of using GIC ITS, so > - no ITS support is required and the 'msi-map' is not required, > - a new 'msi' interrupt is needed. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > > Changes in v6: > - Fix make dt_binding_check and make CHECK_DTBS=y > > Changes in v5: > - Add constraints per device for interrupt-names due to the interrupt is > different from rk3588. > > Changes in v4: > - Fix wrong indentation in dt_binding_check report by Rob > > Changes in v3: > - Fix dtb check broken on rk3588 > - Update commit message > > Changes in v2: > - remove required 'msi-map' > - add interrupt name 'msi' > > .../bindings/pci/rockchip-dw-pcie-common.yaml | 41 ++++++++++++++++++- > .../bindings/pci/rockchip-dw-pcie.yaml | 19 ++++++--- > 2 files changed, 52 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > index cc9adfc7611c..e1ca8e2f35fe 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml > @@ -65,7 +65,11 @@ properties: > tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, > nf_err_rx, f_err_rx, radm_qoverflow > - description: > - eDMA write channel 0 interrupt > + If the matching interrupt name is "msi", then this is the combinded > + MSI line interrupt, which is to support MSI interrupts output to GIC > + controller via GIC SPI interrupt instead of GIC its interrupt. > + If the matching interrupt name is "dma0", then this is the eDMA write > + channel 0 interrupt. > - description: > eDMA write channel 1 interrupt > - description: > @@ -81,7 +85,9 @@ properties: > - const: msg > - const: legacy > - const: err > - - const: dma0 > + - enum: > + - msi > + - dma0 > - const: dma1 > - const: dma2 > - const: dma3 > @@ -123,4 +129,35 @@ required: > > additionalProperties: true > > +anyOf: There is never syntax like that. Where did you find it (so we can fix it)? > + - if: > + properties: > + compatible: > + contains: > + const: rockchip,rk3576-pcie This does not belong to common schema, but to device specific. I don't see this compatible in this common schema at all. > + then: > + properties: interrupts: minItems: 6 maxItems: 6 > + interrupt-names: > + items: > + - const: sys > + - const: pmc > + - const: msg > + - const: legacy > + - const: err Best regards, Krzysztof
On 24/02/2025 08:49, Kever Yang wrote: > rk3576 is using DWC PCIe controller, with msi interrupt directly to GIC > instead of using GIC ITS, so > - no ITS support is required and the 'msi-map' is not required, > - a new 'msi' interrupt is needed. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > > Changes in v6: > - Fix make dt_binding_check and make CHECK_DTBS=y Now I see you already sent v6 and you already received review. Implement previous review and respond to it. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index cc9adfc7611c..e1ca8e2f35fe 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -65,7 +65,11 @@ properties: tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow - description: - eDMA write channel 0 interrupt + If the matching interrupt name is "msi", then this is the combinded + MSI line interrupt, which is to support MSI interrupts output to GIC + controller via GIC SPI interrupt instead of GIC its interrupt. + If the matching interrupt name is "dma0", then this is the eDMA write + channel 0 interrupt. - description: eDMA write channel 1 interrupt - description: @@ -81,7 +85,9 @@ properties: - const: msg - const: legacy - const: err - - const: dma0 + - enum: + - msi + - dma0 - const: dma1 - const: dma2 - const: dma3 @@ -123,4 +129,35 @@ required: additionalProperties: true +anyOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3576-pcie + then: + properties: + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: msi + else: + properties: + interrupt-names: + minItems: 5 + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 + ... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 550d8a684af3..d727502ed822 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -16,16 +16,13 @@ description: |+ PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# - properties: compatible: oneOf: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3576-pcie - rockchip,rk3588-pcie - const: rockchip,rk3568-pcie @@ -71,8 +68,18 @@ properties: vpcie3v3-supply: true -required: - - msi-map +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + - if: + not: + properties: + compatible: + contains: + const: rockchip,rk3576-pcie + then: + required: + - msi-map unevaluatedProperties: false