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[v2,0/3] arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling

Message ID 20250211-topic-sm8650-ddr-bw-scaling-v2-0-a0c950540e68@linaro.org (mailing list archive)
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Series arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling | expand

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Neil Armstrong Feb. 11, 2025, 12:56 p.m. UTC 
Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v2:
- Drop already applied bindings patch
- Link to v1: https://lore.kernel.org/r/20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org

---
Neil Armstrong (3):
      arm64: dts: qcom: sm8650: add OSM L3 node
      arm64: dts: qcom: sm8650: add cpu interconnect nodes
      arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths

 arch/arm64/boot/dts/qcom/sm8650.dtsi | 943 +++++++++++++++++++++++++++++++++++
 1 file changed, 943 insertions(+)
---
base-commit: 808eb958781e4ebb6e9c0962af2e856767e20f45
change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246

Best regards,

Comments

Bjorn Andersson Feb. 25, 2025, 6:18 p.m. UTC | #1 
On Tue, 11 Feb 2025 13:56:36 +0100, Neil Armstrong wrote:
> Add the OSM L3 controller node then add the necessary interconnect
> properties with the appropriate OPP table for each CPU cluster to
> allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
> cluster operating point.
> 
> 

Applied, thanks!

[1/3] arm64: dts: qcom: sm8650: add OSM L3 node
      commit: 62a770da5327910233ff0b0e1989e14feb3d766e
[2/3] arm64: dts: qcom: sm8650: add cpu interconnect nodes
      commit: c9658c3963b8a5ebe488acfa2609fc641a126b60
[3/3] arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths
      commit: c24db2c178578ab069dba8be81ef278854bad74f

Best regards,