diff mbox series

reset: rzg2l-usbphy-ctrl: Correct reset status check

Message ID 20250303190841.179890-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Delegated to: Geert Uytterhoeven
Headers show
Series reset: rzg2l-usbphy-ctrl: Correct reset status check | expand

Commit Message

Prabhakar March 3, 2025, 7:08 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Ensure the reset status check explicitly evaluates whether all bits in
`port_mask` are set. Replace the double negation (`!!`) with an equality
check to prevent incorrect interpretation of partial bit matches as an
asserted reset.

Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver")
Cc: stable@vger.kernel.org
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Biju Das March 4, 2025, 6:43 a.m. UTC | #1 
Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 03 March 2025 19:09
> Subject: [PATCH] reset: rzg2l-usbphy-ctrl: Correct reset status check
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Ensure the reset status check explicitly evaluates whether all bits in `port_mask` are set. Replace
> the double negation (`!!`) with an equality check to prevent incorrect interpretation of partial bit
> matches as an asserted reset.
> 
> Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver")
> Cc: stable@vger.kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> index 8a7f167e405e..6451f621e862 100644
> --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> @@ -88,7 +88,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
> 
>  	port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
> 
> -	return !!(readl(priv->base + RESET) & port_mask);
> +	return (readl(priv->base + RESET) & port_mask) == port_mask;


As per the hardware manual, these status bit is valid only when
Only when sel_pxreset=1.

If sel_pxreset=0, we are reporting invalid status to the caller.

Maybe we should check sel_pxreset while setting it and read it back to
Ensure that it is set to 1 and in this function just check for
phyrst_x bit for reporting status

Cheers,
Biju

>  }
> 
>  static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
> --
> 2.43.0
Prabhakar March 4, 2025, 7:41 a.m. UTC | #2 
Hi Biju,

Thank you for the review.

On Tue, Mar 4, 2025 at 6:43 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 03 March 2025 19:09
> > Subject: [PATCH] reset: rzg2l-usbphy-ctrl: Correct reset status check
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Ensure the reset status check explicitly evaluates whether all bits in `port_mask` are set. Replace
> > the double negation (`!!`) with an equality check to prevent incorrect interpretation of partial bit
> > matches as an asserted reset.
> >
> > Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > index 8a7f167e405e..6451f621e862 100644
> > --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > @@ -88,7 +88,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
> >
> >       port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
> >
> > -     return !!(readl(priv->base + RESET) & port_mask);
> > +     return (readl(priv->base + RESET) & port_mask) == port_mask;
>
>
> As per the hardware manual, these status bit is valid only when
> Only when sel_pxreset=1.
>
> If sel_pxreset=0, we are reporting invalid status to the caller.
>
> Maybe we should check sel_pxreset while setting it and read it back to
> Ensure that it is set to 1 and in this function just check for
> phyrst_x bit for reporting status
>
Ok, I will update it as above and send a v2.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
index 8a7f167e405e..6451f621e862 100644
--- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -88,7 +88,7 @@  static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
 
 	port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
 
-	return !!(readl(priv->base + RESET) & port_mask);
+	return (readl(priv->base + RESET) & port_mask) == port_mask;
 }
 
 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {