| Message ID | 20250225-preset_v6-v7-1-a593f3ef3951@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dwc: Add support for configuring lane equalization presets | expand |
On Tue, Feb 25, 2025 at 05:15:04PM +0530, Krishna Chaitanya Chundru wrote: > Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data > rates used in lane equalization procedure. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> One minor nit below. > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > This patch depends on the this dt binding pull request which got recently > merged: https://github.com/devicetree-org/dt-schema/pull/146 > --- > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 4936fa5b98ff..9a18b8f90145 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > phys = <&pcie3_phy>; > phy-names = "pciephy"; > > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 > + 0x5555 0x5555 0x5555 0x5555>; > + Get rid of the newline between eq-presets-8gts and eq-presets-16gts. - Mani
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4936fa5b98ff..9a18b8f90145 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie3_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie3_opp_table>; status = "disabled"; @@ -3411,6 +3416,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; }; @@ -3538,6 +3547,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3662,6 +3673,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 {