| Message ID | 20250228202655.491035-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: rzv2h-cpg: Add support for static mux clocks and static dividers | expand |
Hi Prabhakar, On Fri, 28 Feb 2025 at 21:27, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Unlike dynamic dividers, static dividers do not have a monitor bit. > Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring > consistency with existing dynamic divider macros. > > Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence > of a monitor bit, allowing the monitoring step to be skipped when > `mon` is set to `CSDIV_NO_MON`. > > Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic > `clk_hw_register_divider_table()` for registering satic dividers > as some of the static dividers require RMW operations. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! I understand this is in preparation of adding GBETH/XSPI clocks, and thus related to "[PATCH 2/4] clk: renesas: rzv2h-cpg: Add support for static dividers"[1]? > --- a/drivers/clk/renesas/rzv2h-cpg.h > +++ b/drivers/clk/renesas/rzv2h-cpg.h > @@ -25,6 +25,14 @@ struct ddiv { > unsigned int monbit:5; > }; > > +/* > + * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, > + * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value > + * `0x1f` to indicate that monitor bits are not supported for static divider > + * clocks. > + */ > +#define CSDIV_NO_MON (0x1f) > + > #define DDIV_PACK(_offset, _shift, _width, _monbit) \ > ((struct ddiv){ \ > .offset = _offset, \ > @@ -130,6 +138,8 @@ enum clk_types { > .parent = _parent, \ > .dtable = _dtable, \ > .flag = CLK_DIVIDER_HIWORD_MASK) > +#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ > + DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) > #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ > DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ > .cfg.smux = _smux_packed, \ However, Biju's patch adds a new composer DEF_SDIV(), and we end up with not using DEF_CSDIV() at all? [1] https://lore.kernel.org/20250303110433.76576-3-biju.das.jz@bp.renesas.com Gr{oetje,eeting}s, Geert
Hi Geert, On Thu, Mar 6, 2025 at 2:43 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, 28 Feb 2025 at 21:27, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Unlike dynamic dividers, static dividers do not have a monitor bit. > > Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring > > consistency with existing dynamic divider macros. > > > > Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence > > of a monitor bit, allowing the monitoring step to be skipped when > > `mon` is set to `CSDIV_NO_MON`. > > > > Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic > > `clk_hw_register_divider_table()` for registering satic dividers > > as some of the static dividers require RMW operations. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > I understand this is in preparation of adding GBETH/XSPI clocks, and > thus related to "[PATCH 2/4] clk: renesas: rzv2h-cpg: Add support for > static dividers"[1]? > I will send out patches for GBETH clocks which will use the DEF_CSDIV() macro. Basically DEF_CSDIV() macro will be used IPs which require RMW operations whereas in case Biju's patch DEF_SDIV() macro will be used IP's which do not need RMW operations. Cheers, Prabhakar
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 6cda865c94fb..60d49ff2f8d3 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -302,6 +302,9 @@ static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon u32 bitmask = BIT(mon); u32 val; + if (mon == CSDIV_NO_MON) + return 0; + return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200); } diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 0ac2db805614..ed7036073b0c 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -25,6 +25,14 @@ struct ddiv { unsigned int monbit:5; }; +/* + * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, + * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value + * `0x1f` to indicate that monitor bits are not supported for static divider + * clocks. + */ +#define CSDIV_NO_MON (0x1f) + #define DDIV_PACK(_offset, _shift, _width, _monbit) \ ((struct ddiv){ \ .offset = _offset, \ @@ -130,6 +138,8 @@ enum clk_types { .parent = _parent, \ .dtable = _dtable, \ .flag = CLK_DIVIDER_HIWORD_MASK) +#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ + DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ .cfg.smux = _smux_packed, \