@@ -18,7 +18,7 @@
#define AFE_BASE_END_OFFSET 8
-static int mtk_regmap_update_bits(struct regmap *map, int reg,
+int mtk_regmap_update_bits(struct regmap *map, int reg,
unsigned int mask,
unsigned int val, int shift)
{
@@ -26,13 +26,16 @@ static int mtk_regmap_update_bits(struct regmap *map, int reg,
return 0;
return regmap_update_bits(map, reg, mask << shift, val << shift);
}
+EXPORT_SYMBOL(mtk_regmap_update_bits);
+
+int mtk_regmap_write(struct regmap *map, int reg, unsigned int val)
-static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val)
{
if (reg < 0)
return 0;
return regmap_write(map, reg, val);
}
+EXPORT_SYMBOL(mtk_regmap_write);
int mtk_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
@@ -459,8 +462,12 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe,
struct mtk_base_afe_memif *memif = &afe->memif[id];
unsigned int mono;
- if (memif->data->mono_shift < 0)
- return 0;
+ dev_info(afe->dev, "%s(), id: %d, channel: %d\n", __func__, id, channel);
+ mono = memif->data->mono_invert ^ (channel == 1);
+
+ if (memif->data->mono_shift > 0)
+ mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
+ 0x1, mono, memif->data->mono_shift);
if (memif->data->quad_ch_mask) {
unsigned int quad_ch = (channel == 4) ? 1 : 0;
@@ -470,11 +477,6 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe,
quad_ch, memif->data->quad_ch_shift);
}
- if (memif->data->mono_invert)
- mono = (channel == 1) ? 0 : 1;
- else
- mono = (channel == 1) ? 1 : 0;
-
/* for specific configuration of memif mono mode */
if (memif->data->int_odd_flag_reg)
mtk_regmap_update_bits(afe->regmap,
@@ -482,8 +484,14 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe,
1, mono,
memif->data->int_odd_flag_shift);
- return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
- 1, mono, memif->data->mono_shift);
+ if (memif->data->ch_num_maskbit) {
+ dev_info(afe->dev, "%s(), set ch num id: %d, channel: %d\n", __func__, id, channel);
+ mtk_regmap_update_bits(afe->regmap, memif->data->ch_num_reg,
+ memif->data->ch_num_maskbit,
+ channel, memif->data->ch_num_shift);
+ }
+
+ return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_channel);
@@ -12,7 +12,13 @@
struct snd_soc_dai_ops;
struct mtk_base_afe;
struct mtk_base_afe_memif;
+struct mtk_base_irq_data;
+int mtk_regmap_update_bits(struct regmap *map, int reg,
+ unsigned int mask, unsigned int val,
+ int shift);
+int mtk_regmap_write(struct regmap *map, int reg,
+ unsigned int val);
int mtk_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
void mtk_afe_fe_shutdown(struct snd_pcm_substream *substream,
@@ -53,9 +53,11 @@ struct mtk_base_memif_data {
int enable_reg;
int enable_shift;
int hd_reg;
+ int hd_mask;
int hd_shift;
int hd_align_reg;
int hd_align_mshift;
+ int hd_msb_shift;
int msb_reg;
int msb_shift;
int msb_end_reg;
@@ -65,6 +67,10 @@ struct mtk_base_memif_data {
int ch_num_reg;
int ch_num_shift;
int ch_num_maskbit;
+ /* VUL 24~26 only for CM2 */
+ int out_on_use_reg;
+ int out_on_use_mask;
+ int out_on_use_shift;
/* playback memif only */
int pbuf_reg;
int pbuf_mask;
@@ -72,6 +78,9 @@ struct mtk_base_memif_data {
int minlen_reg;
int minlen_mask;
int minlen_shift;
+ int maxlen_reg;
+ int maxlen_mask;
+ int maxlen_shift;
};
struct mtk_base_irq_data {
@@ -87,6 +96,10 @@ struct mtk_base_irq_data {
int irq_clr_reg;
int irq_clr_shift;
int irq_status_shift;
+ int irq_ap_en_reg;
+ int irq_ap_en_shift;
+ int irq_scp_en_reg;
+ int irq_scp_en_shift;
};
struct device;