| Message ID | 20250305194612.47171-1-ziyao@disroot.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support SD/SDIO controllers on RK3528 | expand |
Hi, > + sdio0: mmc@ffc10000 { > + compatible = "rockchip,rk3528-dw-mshc", > + "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xffc10000 0x0 0x4000>; > + clocks = <&cru HCLK_SDIO0>, > + <&cru CCLK_SRC_SDIO0>, > + <&cru SCLK_SDIO0_DRV>, > + <&cru SCLK_SDIO0_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > + max-frequency = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, > + <&sdio0_det>, <&sdio0_pwren>; The sdio module is usually "non-removable", no need det, and pwren may be other gpio (use mmc-pwrseq). So it should be `pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;` > + resets = <&cru SRST_H_SDIO0>; > + reset-names = "reset"; > + status = "disabled"; > + }; > + > + sdio1: mmc@ffc20000 { > + compatible = "rockchip,rk3528-dw-mshc", > + "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xffc20000 0x0 0x4000>; > + clocks = <&cru HCLK_SDIO1>, > + <&cru CCLK_SRC_SDIO1>, > + <&cru SCLK_SDIO1_DRV>, > + <&cru SCLK_SDIO1_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + max-frequency = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, > + <&sdio1_det>, <&sdio1_pwren>; Same here. > + resets = <&cru SRST_H_SDIO1>; > + reset-names = "reset"; > + status = "disabled"; > + }; Thanks, Chukun
On Thu, Mar 06, 2025 at 10:00:09PM +0800, Chukun Pan wrote: > Hi, > > > + sdio0: mmc@ffc10000 { > > + compatible = "rockchip,rk3528-dw-mshc", > > + "rockchip,rk3288-dw-mshc"; > > + reg = <0x0 0xffc10000 0x0 0x4000>; > > + clocks = <&cru HCLK_SDIO0>, > > + <&cru CCLK_SRC_SDIO0>, > > + <&cru SCLK_SDIO0_DRV>, > > + <&cru SCLK_SDIO0_SAMPLE>; > > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > > + fifo-depth = <0x100>; > > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > > + max-frequency = <150000000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, > > + <&sdio0_det>, <&sdio0_pwren>; > > The sdio module is usually "non-removable", no need det, > and pwren may be other gpio (use mmc-pwrseq). So it should > be `pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;` This doesn't affect the fact that these two pins are assigned as functional pins for SDIO0, as pointed out by the datasheet[1]. But with more digging, I found the reference design[2] of Rockchip actually uses the two pins as normal GPIOs. This is more obvious in downstream devicetree of an EVB[3]. Most of the existing boards (Radxa 2A, ArmSOM Sige 1) follow the reference design. For me, it's kind of surprising that the SDIO IP functions with two functional pins assigned as different modes. I'm not sure whether we should apply pin configuration for these two pins in the SoC devicetree. Jonas, what do you think about it? > > + resets = <&cru SRST_H_SDIO0>; > > + reset-names = "reset"; > > + status = "disabled"; > > + }; > > + > > + sdio1: mmc@ffc20000 { > > + compatible = "rockchip,rk3528-dw-mshc", > > + "rockchip,rk3288-dw-mshc"; > > + reg = <0x0 0xffc20000 0x0 0x4000>; > > + clocks = <&cru HCLK_SDIO1>, > > + <&cru CCLK_SRC_SDIO1>, > > + <&cru SCLK_SDIO1_DRV>, > > + <&cru SCLK_SDIO1_SAMPLE>; > > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > > + fifo-depth = <0x100>; > > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > > + max-frequency = <150000000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, > > + <&sdio1_det>, <&sdio1_pwren>; > > Same here. > > > + resets = <&cru SRST_H_SDIO1>; > > + reset-names = "reset"; > > + status = "disabled"; > > + }; > > Thanks, > Chukun > > -- > 2.25.1 > Best regards, Yao Zi [1]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/Rockchip%C2%A0RK3528%C2%A0Datasheet%C2%A0V1.0-20230522.pdf [2]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/RK3528_BOX_REF_V10_20230525.pdf [3]: https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dtsi#L128
On 2025-03-06 17:43, Yao Zi wrote: > On Thu, Mar 06, 2025 at 10:00:09PM +0800, Chukun Pan wrote: >> Hi, >> >>> + sdio0: mmc@ffc10000 { >>> + compatible = "rockchip,rk3528-dw-mshc", >>> + "rockchip,rk3288-dw-mshc"; >>> + reg = <0x0 0xffc10000 0x0 0x4000>; >>> + clocks = <&cru HCLK_SDIO0>, >>> + <&cru CCLK_SRC_SDIO0>, >>> + <&cru SCLK_SDIO0_DRV>, >>> + <&cru SCLK_SDIO0_SAMPLE>; >>> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; >>> + fifo-depth = <0x100>; >>> + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; >>> + max-frequency = <150000000>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, >>> + <&sdio0_det>, <&sdio0_pwren>; >> >> The sdio module is usually "non-removable", no need det, >> and pwren may be other gpio (use mmc-pwrseq). So it should >> be `pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;` > > This doesn't affect the fact that these two pins are assigned as > functional pins for SDIO0, as pointed out by the datasheet[1]. > > But with more digging, I found the reference design[2] of Rockchip > actually uses the two pins as normal GPIOs. This is more obvious in > downstream devicetree of an EVB[3]. Most of the existing boards (Radxa > 2A, ArmSOM Sige 1) follow the reference design. > > For me, it's kind of surprising that the SDIO IP functions with two > functional pins assigned as different modes. I'm not sure whether we > should apply pin configuration for these two pins in the SoC devicetree. > Jonas, what do you think about it? I think it make sense to match the pins used by reference boards, i.e. the pinconf most likely to be used by majority of boards that will use the sdio interface. Of my RK3528 boards, only ArmSoM Sige1 use sdio for onboard wifi and there I currently have following in my work-in-progress board DT [4]: pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, <&clkm1_32k_out>; The Radxa ROCK 2A/2F seem to use USB for wifi/bt. [4] https://github.com/Kwiboo/linux-rockchip/blob/next-20250305-rk3528/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts Regards, Jonas > >>> + resets = <&cru SRST_H_SDIO0>; >>> + reset-names = "reset"; >>> + status = "disabled"; >>> + }; >>> + >>> + sdio1: mmc@ffc20000 { >>> + compatible = "rockchip,rk3528-dw-mshc", >>> + "rockchip,rk3288-dw-mshc"; >>> + reg = <0x0 0xffc20000 0x0 0x4000>; >>> + clocks = <&cru HCLK_SDIO1>, >>> + <&cru CCLK_SRC_SDIO1>, >>> + <&cru SCLK_SDIO1_DRV>, >>> + <&cru SCLK_SDIO1_SAMPLE>; >>> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; >>> + fifo-depth = <0x100>; >>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; >>> + max-frequency = <150000000>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, >>> + <&sdio1_det>, <&sdio1_pwren>; >> >> Same here. >> >>> + resets = <&cru SRST_H_SDIO1>; >>> + reset-names = "reset"; >>> + status = "disabled"; >>> + }; >> >> Thanks, >> Chukun >> >> -- >> 2.25.1 >> > > Best regards, > Yao Zi > > [1]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/Rockchip%C2%A0RK3528%C2%A0Datasheet%C2%A0V1.0-20230522.pdf > [2]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/RK3528_BOX_REF_V10_20230525.pdf > [3]: https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dtsi#L128
On Fri, Mar 07, 2025 at 12:05:16AM +0100, Jonas Karlman wrote: > On 2025-03-06 17:43, Yao Zi wrote: > > On Thu, Mar 06, 2025 at 10:00:09PM +0800, Chukun Pan wrote: > >> Hi, > >> > >>> + sdio0: mmc@ffc10000 { > >>> + compatible = "rockchip,rk3528-dw-mshc", > >>> + "rockchip,rk3288-dw-mshc"; > >>> + reg = <0x0 0xffc10000 0x0 0x4000>; > >>> + clocks = <&cru HCLK_SDIO0>, > >>> + <&cru CCLK_SRC_SDIO0>, > >>> + <&cru SCLK_SDIO0_DRV>, > >>> + <&cru SCLK_SDIO0_SAMPLE>; > >>> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > >>> + fifo-depth = <0x100>; > >>> + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > >>> + max-frequency = <150000000>; > >>> + pinctrl-names = "default"; > >>> + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, > >>> + <&sdio0_det>, <&sdio0_pwren>; > >> > >> The sdio module is usually "non-removable", no need det, > >> and pwren may be other gpio (use mmc-pwrseq). So it should > >> be `pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;` > > > > This doesn't affect the fact that these two pins are assigned as > > functional pins for SDIO0, as pointed out by the datasheet[1]. > > > > But with more digging, I found the reference design[2] of Rockchip > > actually uses the two pins as normal GPIOs. This is more obvious in > > downstream devicetree of an EVB[3]. Most of the existing boards (Radxa > > 2A, ArmSOM Sige 1) follow the reference design. > > > > For me, it's kind of surprising that the SDIO IP functions with two > > functional pins assigned as different modes. I'm not sure whether we > > should apply pin configuration for these two pins in the SoC devicetree. > > Jonas, what do you think about it? > > I think it make sense to match the pins used by reference boards, i.e. > the pinconf most likely to be used by majority of boards that will use > the sdio interface. Thanks, will take it. > Of my RK3528 boards, only ArmSoM Sige1 use sdio for onboard wifi and > there I currently have following in my work-in-progress board DT [4]: > > pinctrl-names = "default"; > pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, <&clkm1_32k_out>; > > The Radxa ROCK 2A/2F seem to use USB for wifi/bt. > > [4] https://github.com/Kwiboo/linux-rockchip/blob/next-20250305-rk3528/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts > > Regards, > Jonas > > > > >>> + resets = <&cru SRST_H_SDIO0>; > >>> + reset-names = "reset"; > >>> + status = "disabled"; > >>> + }; > >>> + > >>> + sdio1: mmc@ffc20000 { > >>> + compatible = "rockchip,rk3528-dw-mshc", > >>> + "rockchip,rk3288-dw-mshc"; > >>> + reg = <0x0 0xffc20000 0x0 0x4000>; > >>> + clocks = <&cru HCLK_SDIO1>, > >>> + <&cru CCLK_SRC_SDIO1>, > >>> + <&cru SCLK_SDIO1_DRV>, > >>> + <&cru SCLK_SDIO1_SAMPLE>; > >>> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > >>> + fifo-depth = <0x100>; > >>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > >>> + max-frequency = <150000000>; > >>> + pinctrl-names = "default"; > >>> + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, > >>> + <&sdio1_det>, <&sdio1_pwren>; > >> > >> Same here. > >> > >>> + resets = <&cru SRST_H_SDIO1>; > >>> + reset-names = "reset"; > >>> + status = "disabled"; > >>> + }; > >> > >> Thanks, > >> Chukun > >> > >> -- > >> 2.25.1 > >> > > > > Best regards, > > Yao Zi > > > > [1]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/Rockchip%C2%A0RK3528%C2%A0Datasheet%C2%A0V1.0-20230522.pdf > > [2]: https://github.com/DeciHD/rockchip_docs/blob/main/rk3528/RK3528_BOX_REF_V10_20230525.pdf > > [3]: https://github.com/rockchip-linux/kernel/blob/604cec4004abe5a96c734f2fab7b74809d2d742f/arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10.dtsi#L128 > Best regards, Yao Zi
Hi Yao Zi, On 2025-03-05 20:46, Yao Zi wrote: > RK3528 features two SDIO controllers and one SD/MMC controller, describe > them in devicetree. Since their sample and drive clocks are located in > the VO and VPU GRFs, corresponding syscons are added to make these > clocks available. > > Signed-off-by: Yao Zi <ziyao@disroot.org> > --- > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 70 ++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > index d3e2a64ff2d5..363023314e9c 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > @@ -130,6 +130,16 @@ gic: interrupt-controller@fed01000 { > #interrupt-cells = <3>; > }; > > + vpu_grf: syscon@ff340000 { > + compatible = "rockchip,rk3528-vpu-grf", "syscon"; > + reg = <0x0 0xff340000 0x0 0x8000>; > + }; > + > + vo_grf: syscon@ff360000 { > + compatible = "rockchip,rk3528-vo-grf", "syscon"; > + reg = <0x0 0xff360000 0x0 0x10000>; > + }; > + > cru: clock-controller@ff4a0000 { > compatible = "rockchip,rk3528-cru"; > reg = <0x0 0xff4a0000 0x0 0x30000>; > @@ -274,6 +284,66 @@ saradc: adc@ffae0000 { > resets = <&cru SRST_P_SARADC>; > reset-names = "saradc-apb"; > #io-channel-cells = <1>; > + }; Look like this patch accidentally drops status = "disabled" from the adc@ffae0000 node. Regards, Jonas > + > + sdio0: mmc@ffc10000 { > + compatible = "rockchip,rk3528-dw-mshc", > + "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xffc10000 0x0 0x4000>; > + clocks = <&cru HCLK_SDIO0>, > + <&cru CCLK_SRC_SDIO0>, > + <&cru SCLK_SDIO0_DRV>, > + <&cru SCLK_SDIO0_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; > + max-frequency = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, > + <&sdio0_det>, <&sdio0_pwren>; > + resets = <&cru SRST_H_SDIO0>; > + reset-names = "reset"; > + status = "disabled"; > + }; > + > + sdio1: mmc@ffc20000 { > + compatible = "rockchip,rk3528-dw-mshc", > + "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xffc20000 0x0 0x4000>; > + clocks = <&cru HCLK_SDIO1>, > + <&cru CCLK_SRC_SDIO1>, > + <&cru SCLK_SDIO1_DRV>, > + <&cru SCLK_SDIO1_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + max-frequency = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, > + <&sdio1_det>, <&sdio1_pwren>; > + resets = <&cru SRST_H_SDIO1>; > + reset-names = "reset"; > + status = "disabled"; > + }; > + > + sdmmc: mmc@ffc30000 { > + compatible = "rockchip,rk3528-dw-mshc", > + "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xffc30000 0x0 0x4000>; > + clocks = <&cru HCLK_SDMMC0>, > + <&cru CCLK_SRC_SDMMC0>, > + <&cru SCLK_SDMMC_DRV>, > + <&cru SCLK_SDMMC_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + max-frequency = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, > + <&sdmmc_det>; > + resets = <&cru SRST_H_SDMMC0>; > + reset-names = "reset"; > + rockchip,default-sample-phase = <90>; > status = "disabled"; > }; >
On Sat, Mar 08, 2025 at 12:22:48AM +0100, Jonas Karlman wrote: > Hi Yao Zi, > > On 2025-03-05 20:46, Yao Zi wrote: > > RK3528 features two SDIO controllers and one SD/MMC controller, describe > > them in devicetree. Since their sample and drive clocks are located in > > the VO and VPU GRFs, corresponding syscons are added to make these > > clocks available. > > > > Signed-off-by: Yao Zi <ziyao@disroot.org> > > --- > > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 70 ++++++++++++++++++++++++ > > 1 file changed, 70 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > > index d3e2a64ff2d5..363023314e9c 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > > @@ -130,6 +130,16 @@ gic: interrupt-controller@fed01000 { > > #interrupt-cells = <3>; > > }; > > > > + vpu_grf: syscon@ff340000 { > > + compatible = "rockchip,rk3528-vpu-grf", "syscon"; > > + reg = <0x0 0xff340000 0x0 0x8000>; > > + }; > > + > > + vo_grf: syscon@ff360000 { > > + compatible = "rockchip,rk3528-vo-grf", "syscon"; > > + reg = <0x0 0xff360000 0x0 0x10000>; > > + }; > > + > > cru: clock-controller@ff4a0000 { > > compatible = "rockchip,rk3528-cru"; > > reg = <0x0 0xff4a0000 0x0 0x30000>; > > @@ -274,6 +284,66 @@ saradc: adc@ffae0000 { > > resets = <&cru SRST_P_SARADC>; > > reset-names = "saradc-apb"; > > #io-channel-cells = <1>; > > + }; > > Look like this patch accidentally drops status = "disabled" from the > adc@ffae0000 node. It's a mistake during rebasing, I'll fix it in v3. > Regards, > Jonas Thanks, Yao Zi
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index d3e2a64ff2d5..363023314e9c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -130,6 +130,16 @@ gic: interrupt-controller@fed01000 { #interrupt-cells = <3>; }; + vpu_grf: syscon@ff340000 { + compatible = "rockchip,rk3528-vpu-grf", "syscon"; + reg = <0x0 0xff340000 0x0 0x8000>; + }; + + vo_grf: syscon@ff360000 { + compatible = "rockchip,rk3528-vo-grf", "syscon"; + reg = <0x0 0xff360000 0x0 0x10000>; + }; + cru: clock-controller@ff4a0000 { compatible = "rockchip,rk3528-cru"; reg = <0x0 0xff4a0000 0x0 0x30000>; @@ -274,6 +284,66 @@ saradc: adc@ffae0000 { resets = <&cru SRST_P_SARADC>; reset-names = "saradc-apb"; #io-channel-cells = <1>; + }; + + sdio0: mmc@ffc10000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc10000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO0>, + <&cru CCLK_SRC_SDIO0>, + <&cru SCLK_SDIO0_DRV>, + <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>, + <&sdio0_det>, <&sdio0_pwren>; + resets = <&cru SRST_H_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc20000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO1>, + <&cru CCLK_SRC_SDIO1>, + <&cru SCLK_SDIO1_DRV>, + <&cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>, + <&sdio1_det>, <&sdio1_pwren>; + resets = <&cru SRST_H_SDIO1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC0>, + <&cru CCLK_SRC_SDMMC0>, + <&cru SCLK_SDMMC_DRV>, + <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, + <&sdmmc_det>; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + rockchip,default-sample-phase = <90>; status = "disabled"; };
RK3528 features two SDIO controllers and one SD/MMC controller, describe them in devicetree. Since their sample and drive clocks are located in the VO and VPU GRFs, corresponding syscons are added to make these clocks available. Signed-off-by: Yao Zi <ziyao@disroot.org> --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+)