Message ID | 20250306-iio-driver-ad4052-v1-4-2badad30116c@analog.com (mailing list archive) |
---|---|
State | Changes Requested |
Headers | show |
Series | Add support for AD4052 device family | expand |
Hi Jorge, kernel test robot noticed the following build warnings: [auto build test WARNING on aac287ec80d71a7ab7e44c936a434625417c3e30] url: https://github.com/intel-lab-lkp/linux/commits/Jorge-Marques/iio-code-mark-iio_dev-as-const-in-iio_buffer_enabled/20250306-220719 base: aac287ec80d71a7ab7e44c936a434625417c3e30 patch link: https://lore.kernel.org/r/20250306-iio-driver-ad4052-v1-4-2badad30116c%40analog.com patch subject: [PATCH 4/4] iio: adc: add support for ad4052 config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20250307/202503071916.STHJTSlp-lkp@intel.com/config) compiler: sh4-linux-gcc (GCC) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250307/202503071916.STHJTSlp-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202503071916.STHJTSlp-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/iio/adc/ad4052.c:239:18: warning: 'ad4052_sample_rate_avail' defined but not used [-Wunused-const-variable=] 239 | static const int ad4052_sample_rate_avail[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/iio/adc/ad4052.c:214:41: warning: 'ad4052_regmap_wr_table' defined but not used [-Wunused-const-variable=] 214 | static const struct regmap_access_table ad4052_regmap_wr_table = { | ^~~~~~~~~~~~~~~~~~~~~~ >> drivers/iio/adc/ad4052.c:201:41: warning: 'ad4052_regmap_rd_table' defined but not used [-Wunused-const-variable=] 201 | static const struct regmap_access_table ad4052_regmap_rd_table = { | ^~~~~~~~~~~~~~~~~~~~~~ vim +/ad4052_sample_rate_avail +239 drivers/iio/adc/ad4052.c 200 > 201 static const struct regmap_access_table ad4052_regmap_rd_table = { 202 .yes_ranges = ad4052_regmap_rd_ranges, 203 .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_rd_ranges), 204 }; 205 206 static const struct regmap_range ad4052_regmap_wr_ranges[] = { 207 regmap_reg_range(AD4052_REG_INTERFACE_CONFIG_A, AD4052_REG_DEVICE_CONFIG), 208 regmap_reg_range(AD4052_REG_SCRATCH_PAD, AD4052_REG_SCRATCH_PAD), 209 regmap_reg_range(AD4052_REG_STREAM_MODE, AD4052_REG_INTERFACE_STATUS), 210 regmap_reg_range(AD4052_REG_MODE_SET, AD4052_REG_MON_VAL), 211 regmap_reg_range(AD4052_REG_FUSE_CRC, AD4052_REG_DEVICE_STATUS), 212 }; 213 > 214 static const struct regmap_access_table ad4052_regmap_wr_table = { 215 .yes_ranges = ad4052_regmap_wr_ranges, 216 .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_wr_ranges), 217 }; 218 219 static const struct iio_event_spec ad4052_events[] = { 220 { 221 .type = IIO_EV_TYPE_THRESH, 222 .dir = IIO_EV_DIR_EITHER, 223 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE) 224 }, 225 { 226 .type = IIO_EV_TYPE_THRESH, 227 .dir = IIO_EV_DIR_RISING, 228 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 229 BIT(IIO_EV_INFO_HYSTERESIS) 230 }, 231 { 232 .type = IIO_EV_TYPE_THRESH, 233 .dir = IIO_EV_DIR_FALLING, 234 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 235 BIT(IIO_EV_INFO_HYSTERESIS) 236 } 237 }; 238 > 239 static const int ad4052_sample_rate_avail[] = { 240 2000000, 1000000, 300000, 100000, 33300, 241 10000, 3000, 500, 333, 250, 200, 242 166, 140, 125, 111 243 }; 244
Hi Jorge, kernel test robot noticed the following build warnings: [auto build test WARNING on aac287ec80d71a7ab7e44c936a434625417c3e30] url: https://github.com/intel-lab-lkp/linux/commits/Jorge-Marques/iio-code-mark-iio_dev-as-const-in-iio_buffer_enabled/20250306-220719 base: aac287ec80d71a7ab7e44c936a434625417c3e30 patch link: https://lore.kernel.org/r/20250306-iio-driver-ad4052-v1-4-2badad30116c%40analog.com patch subject: [PATCH 4/4] iio: adc: add support for ad4052 config: powerpc-randconfig-r132-20250307 (https://download.01.org/0day-ci/archive/20250307/202503072008.ysqhEBaX-lkp@intel.com/config) compiler: powerpc-linux-gcc (GCC) 14.2.0 reproduce: (https://download.01.org/0day-ci/archive/20250307/202503072008.ysqhEBaX-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202503072008.ysqhEBaX-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/iio/adc/ad4052.c:357:31: sparse: sparse: symbol 'ad4050_chip_info' was not declared. Should it be static? >> drivers/iio/adc/ad4052.c:366:31: sparse: sparse: symbol 'ad4052_chip_info' was not declared. Should it be static? >> drivers/iio/adc/ad4052.c:375:31: sparse: sparse: symbol 'ad4056_chip_info' was not declared. Should it be static? >> drivers/iio/adc/ad4052.c:384:31: sparse: sparse: symbol 'ad4058_chip_info' was not declared. Should it be static? >> drivers/iio/adc/ad4052.c:711:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected int @@ got restricted __be16 [usertype] d16 @@ drivers/iio/adc/ad4052.c:711:22: sparse: expected int drivers/iio/adc/ad4052.c:711:22: sparse: got restricted __be16 [usertype] d16 >> drivers/iio/adc/ad4052.c:715:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected int @@ got restricted __be32 [usertype] d32 @@ drivers/iio/adc/ad4052.c:715:22: sparse: expected int drivers/iio/adc/ad4052.c:715:22: sparse: got restricted __be32 [usertype] d32 drivers/iio/adc/ad4052.c:912:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected int @@ got restricted __be32 [usertype] d32 @@ drivers/iio/adc/ad4052.c:912:22: sparse: expected int drivers/iio/adc/ad4052.c:912:22: sparse: got restricted __be32 [usertype] d32 >> drivers/iio/adc/ad4052.c:958:33: sparse: sparse: bad assignment (>>=) to restricted __be16 drivers/iio/adc/ad4052.c:251:12: sparse: sparse: context imbalance in 'ad4052_iio_device_claim_direct' - different lock contexts for basic block drivers/iio/adc/ad4052.c:277:9: sparse: sparse: context imbalance in 'ad4052_sample_rate_get' - unexpected unlock drivers/iio/adc/ad4052.c:294:9: sparse: sparse: context imbalance in 'ad4052_sample_rate_set' - unexpected unlock drivers/iio/adc/ad4052.c:780:34: sparse: sparse: context imbalance in 'ad4052_read_raw' - unexpected unlock drivers/iio/adc/ad4052.c:805:34: sparse: sparse: context imbalance in 'ad4052_write_raw' - unexpected unlock drivers/iio/adc/ad4052.c:820:9: sparse: sparse: context imbalance in 'ad4052_read_event_config' - unexpected unlock drivers/iio/adc/ad4052.c:903:42: sparse: sparse: context imbalance in 'ad4052_read_event_value' - unexpected unlock drivers/iio/adc/ad4052.c:971:34: sparse: sparse: context imbalance in 'ad4052_write_event_value' - unexpected unlock drivers/iio/adc/ad4052.c:1055:34: sparse: sparse: context imbalance in 'ad4052_debugfs_reg_access' - unexpected unlock vim +/ad4050_chip_info +357 drivers/iio/adc/ad4052.c 356 > 357 const struct ad4052_chip_info ad4050_chip_info = { 358 .name = "ad4050", 359 .channels = { AD4052_CHAN(12, AD4052_2MSPS) }, 360 .offload_channels = { AD4052_OFFLOAD_CHAN(12, AD4052_2MSPS) }, 361 .prod_id = 0x70, 362 .max_avg = AD4050_MAX_AVG, 363 .grade = AD4052_2MSPS, 364 }; 365 > 366 const struct ad4052_chip_info ad4052_chip_info = { 367 .name = "ad4052", 368 .channels = { AD4052_CHAN(16, AD4052_2MSPS) }, 369 .offload_channels = { AD4052_OFFLOAD_CHAN(16, AD4052_2MSPS) }, 370 .prod_id = 0x72, 371 .max_avg = AD4052_MAX_AVG, 372 .grade = AD4052_2MSPS, 373 }; 374 > 375 const struct ad4052_chip_info ad4056_chip_info = { 376 .name = "ad4056", 377 .channels = { AD4052_CHAN(12, AD4052_500KSPS) }, 378 .offload_channels = { AD4052_OFFLOAD_CHAN(12, AD4052_500KSPS) }, 379 .prod_id = 0x70, 380 .max_avg = AD4050_MAX_AVG, 381 .grade = AD4052_500KSPS, 382 }; 383 > 384 const struct ad4052_chip_info ad4058_chip_info = { 385 .name = "ad4058", 386 .channels = { AD4052_CHAN(16, AD4052_500KSPS) }, 387 .offload_channels = { AD4052_OFFLOAD_CHAN(16, AD4052_500KSPS) }, 388 .prod_id = 0x72, 389 .max_avg = AD4052_MAX_AVG, 390 .grade = AD4052_500KSPS, 391 }; 392
Hi Jorge, kernel test robot noticed the following build warnings: [auto build test WARNING on aac287ec80d71a7ab7e44c936a434625417c3e30] url: https://github.com/intel-lab-lkp/linux/commits/Jorge-Marques/iio-code-mark-iio_dev-as-const-in-iio_buffer_enabled/20250306-220719 base: aac287ec80d71a7ab7e44c936a434625417c3e30 patch link: https://lore.kernel.org/r/20250306-iio-driver-ad4052-v1-4-2badad30116c%40analog.com patch subject: [PATCH 4/4] iio: adc: add support for ad4052 config: um-randconfig-r073-20250307 (https://download.01.org/0day-ci/archive/20250308/202503080031.APfLdyiz-lkp@intel.com/config) compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250308/202503080031.APfLdyiz-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202503080031.APfLdyiz-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from drivers/iio/adc/ad4052.c:14: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from arch/um/include/asm/hardirq.h:5: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:14: In file included from arch/um/include/asm/io.h:24: include/asm-generic/io.h:549:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 549 | val = __raw_readb(PCI_IOBASE + addr); | ~~~~~~~~~~ ^ include/asm-generic/io.h:567:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 567 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); | ~~~~~~~~~~ ^ include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu' 37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) | ^ In file included from drivers/iio/adc/ad4052.c:14: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from arch/um/include/asm/hardirq.h:5: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:14: In file included from arch/um/include/asm/io.h:24: include/asm-generic/io.h:585:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 585 | val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr)); | ~~~~~~~~~~ ^ include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu' 35 | #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) | ^ In file included from drivers/iio/adc/ad4052.c:14: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from arch/um/include/asm/hardirq.h:5: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:14: In file included from arch/um/include/asm/io.h:24: include/asm-generic/io.h:601:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 601 | __raw_writeb(value, PCI_IOBASE + addr); | ~~~~~~~~~~ ^ include/asm-generic/io.h:616:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 616 | __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr); | ~~~~~~~~~~ ^ include/asm-generic/io.h:631:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 631 | __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr); | ~~~~~~~~~~ ^ include/asm-generic/io.h:724:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 724 | readsb(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ include/asm-generic/io.h:737:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 737 | readsw(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ include/asm-generic/io.h:750:20: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 750 | readsl(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ include/asm-generic/io.h:764:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 764 | writesb(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ include/asm-generic/io.h:778:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 778 | writesw(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ include/asm-generic/io.h:792:21: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] 792 | writesl(PCI_IOBASE + addr, buffer, count); | ~~~~~~~~~~ ^ >> drivers/iio/adc/ad4052.c:201:41: warning: unused variable 'ad4052_regmap_rd_table' [-Wunused-const-variable] 201 | static const struct regmap_access_table ad4052_regmap_rd_table = { | ^~~~~~~~~~~~~~~~~~~~~~ >> drivers/iio/adc/ad4052.c:214:41: warning: unused variable 'ad4052_regmap_wr_table' [-Wunused-const-variable] 214 | static const struct regmap_access_table ad4052_regmap_wr_table = { | ^~~~~~~~~~~~~~~~~~~~~~ >> drivers/iio/adc/ad4052.c:239:18: warning: unused variable 'ad4052_sample_rate_avail' [-Wunused-const-variable] 239 | static const int ad4052_sample_rate_avail[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~ 15 warnings generated. vim +/ad4052_regmap_rd_table +201 drivers/iio/adc/ad4052.c 200 > 201 static const struct regmap_access_table ad4052_regmap_rd_table = { 202 .yes_ranges = ad4052_regmap_rd_ranges, 203 .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_rd_ranges), 204 }; 205 206 static const struct regmap_range ad4052_regmap_wr_ranges[] = { 207 regmap_reg_range(AD4052_REG_INTERFACE_CONFIG_A, AD4052_REG_DEVICE_CONFIG), 208 regmap_reg_range(AD4052_REG_SCRATCH_PAD, AD4052_REG_SCRATCH_PAD), 209 regmap_reg_range(AD4052_REG_STREAM_MODE, AD4052_REG_INTERFACE_STATUS), 210 regmap_reg_range(AD4052_REG_MODE_SET, AD4052_REG_MON_VAL), 211 regmap_reg_range(AD4052_REG_FUSE_CRC, AD4052_REG_DEVICE_STATUS), 212 }; 213 > 214 static const struct regmap_access_table ad4052_regmap_wr_table = { 215 .yes_ranges = ad4052_regmap_wr_ranges, 216 .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_wr_ranges), 217 }; 218 219 static const struct iio_event_spec ad4052_events[] = { 220 { 221 .type = IIO_EV_TYPE_THRESH, 222 .dir = IIO_EV_DIR_EITHER, 223 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE) 224 }, 225 { 226 .type = IIO_EV_TYPE_THRESH, 227 .dir = IIO_EV_DIR_RISING, 228 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 229 BIT(IIO_EV_INFO_HYSTERESIS) 230 }, 231 { 232 .type = IIO_EV_TYPE_THRESH, 233 .dir = IIO_EV_DIR_FALLING, 234 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 235 BIT(IIO_EV_INFO_HYSTERESIS) 236 } 237 }; 238 > 239 static const int ad4052_sample_rate_avail[] = { 240 2000000, 1000000, 300000, 100000, 33300, 241 10000, 3000, 500, 333, 250, 200, 242 166, 140, 125, 111 243 }; 244
On Thu, 6 Mar 2025 15:03:17 +0100 Jorge Marques <jorge.marques@analog.com> wrote: > The AD4052/AD4058/AD4050/AD4056 are versatile, 16-bit/12-bit, > successive approximation register (SAR) analog-to-digital converter (ADC) > that enables low-power, high-density data acquisition solutions without > sacrificing precision. > This ADC offers a unique balance of performance and power efficiency, > plus innovative features for seamlessly switching between high-resolution > and low-power modes tailored to the immediate needs of the system. > The AD4052/AD4058/AD4050/AD4056 are ideal for battery-powered, > compact data acquisition and edge sensing applications. > > Signed-off-by: Jorge Marques <jorge.marques@analog.com> Hi Jorge Various fairly minor comments inline. Jonathan > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > index 27413516216cb3f83cf1d995b9ffc22bf01776a4..f518dadbdd3a6b0543d0b78206fcbc203898454c 100644 > --- a/drivers/iio/adc/Kconfig > +++ b/drivers/iio/adc/Kconfig > @@ -62,6 +62,20 @@ config AD4130 > To compile this driver as a module, choose M here: the module will be > called ad4130. > > +config AD4052 Aim for alphanumeric order so this should at least be before AD4130 > + tristate "Analog Devices AD4052 Driver" > + depends on SPI > + select SPI_OFFLOAD > + select IIO_BUFFER > + select IIO_BUFFER_DMAENGINE > + select REGMAP_SPI > + help > + Say yes here to build support for Analog Devices AD4052 SPI analog > + to digital converters (ADC). > + > + To compile this driver as a module, choose M here: the module will be > + called ad4052. > + > diff --git a/drivers/iio/adc/ad4052.c b/drivers/iio/adc/ad4052.c > new file mode 100644 > index 0000000000000000000000000000000000000000..29452963fb15ab1b11e3a2fc59c34a2579f25910 > --- /dev/null > +++ b/drivers/iio/adc/ad4052.c > @@ -0,0 +1,1289 @@ ... > +#define AD4052_REG_FUSE_CRC 0x40 > +#define AD4052_REG_DEVICE_STATUS 0x41 > +#define AD4052_REG_MIN_SAMPLE 0x45 > +#define AD4052_MAX_REG 0x45 > +/* GP_CONFIG */ Where possible it makes for easier to follow code if the field defines include what register they are in rather than relying on comments. e.g. #define AD4052_GP_CONFIG_MODE_MASK(x) etc > +#define AD4052_GP_MODE_MSK(x) (GENMASK(2, 0) << (x) * 4) Macro is a bit too 'clever'. I think it would easier to just have AD4052_GP_CONFIG_GP0_MODE_MSK GENMMSK(2, 0) AD4052_GP_CONFIG_GP1_MODE_MSK GENMASK(6, 4) > +/* INTR_CONFIG */ > +#define AD4052_INTR_EN_MSK(x) (GENMASK(1, 0) << (x) * 4) Similar for this one. > +/* ADC_MODES */ > +#define AD4052_DATA_FORMAT BIT(7) > +/* DEVICE_CONFIG */ > +#define AD4052_POWER_MODE_MSK GENMASK(1, 0) > +#define AD4052_LOW_POWER_MODE 3 > +/* DEVICE_STATUS */ > +#define AD4052_DEVICE_RESET BIT(6) > +#define AD4052_THRESH_OVERRUN BIT(4) > +#define AD4052_MAX_FLAG BIT(3) > +#define AD4052_MIN_FLAG BIT(2) > +#define AD4052_EVENT_CLEAR (AD4052_THRESH_OVERRUN | AD4052_MAX_FLAG | AD4052_MIN_FLAG) Wrap the define with \ to break the line. > +/* TIMER_CONFIG */ > +#define AD4052_FS_MASK GENMASK(7, 4) > +#define AD4052_300KSPS 0x2 > + > +#define AD4052_SPI_VENDOR 0x0456 > + > +#define AD4050_MAX_AVG 0x7 > +#define AD4052_MAX_AVG 0xB > +#define AD4052_CHECK_OVERSAMPLING(x, y) ({typeof(y) y_ = (y); \ > + ((y_) < 0 || (y_) > BIT((x) + 1)); }) Don't have single use macros like these. Better to have the code inline where we can see what it is doing. > +#define AD4052_MAX_RATE(x) ((x) == AD4052_500KSPS ? 500000 : 2000000) > +#define AD4052_CHECK_RATE(x, y) ({typeof(y) y_ = (y); \ > + ((y_) > AD4052_MAX_RATE(x) || (y_) <= 0); }) > +#define AD4052_FS_OFFSET(g) ((g) == AD4052_500KSPS ? 2 : 0) > +#define AD4052_FS(g) (&ad4052_sample_rates[AD4052_FS_OFFSET(g)]) > +#define AD4052_FS_LEN(g) (ARRAY_SIZE(ad4052_sample_rates) - (AD4052_FS_OFFSET(g))) ... > +static const int ad4052_sample_rate_avail[] = { > + 2000000, 1000000, 300000, 100000, 33300, > + 10000, 3000, 500, 333, 250, 200, > + 166, 140, 125, 111 trailing comma missing > +}; > + > +static const char *const ad4052_sample_rates[] = { > + "2000000", "1000000", "300000", "100000", "33300", > + "10000", "3000", "500", "333", "250", "200", > + "166", "140", "124", "111", Not sure why this can't be done with read_avail and the values above. > +}; > + > +static int ad4052_iio_device_claim_direct(struct iio_dev *indio_dev, > + struct ad4052_state *st) > +{ > + if (!iio_device_claim_direct(indio_dev)) > + return false; This might stretch sparses ability to keep track or __acquire / __release. Make sure to check that with a C=1 build. If the cond_acquires stuff is merged into sparse, this may need a revisit for markings. > + > + /** Not kernel-doc, so /* > + * If the device is in monitor mode, no register access is allowed, > + * since it would put the device back in configuration mode. > + */ > + if (st->wait_event) { > + iio_device_release_direct(indio_dev); > + return false; > + } > + return true; > +} > + > +static int ad4052_sample_rate_get(struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + int ret, val; > + > + if (!ad4052_iio_device_claim_direct(indio_dev, st)) > + return -EBUSY; > + > + ret = regmap_read(st->regmap, AD4052_REG_TIMER_CONFIG, &val); > + val = FIELD_GET(AD4052_FS_MASK, val); I don't really like the double use of the val variable as it loses meaning we could otherwise provide in the variable naming. > + > + iio_device_release_direct(indio_dev); > + return ret ? ret : val - AD4052_FS_OFFSET(st->chip->grade); > +} > + > +static int ad4052_sample_rate_set(struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan, > + unsigned int val) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + int ret; > + > + if (!ad4052_iio_device_claim_direct(indio_dev, st)) > + return -EBUSY; > + > + val += AD4052_FS_OFFSET(st->chip->grade); > + val = FIELD_PREP(AD4052_FS_MASK, val); Using val for two different things here. I'd avoid that by just having this last line merged with the next one. > + ret = regmap_write(st->regmap, AD4052_REG_TIMER_CONFIG, val); > + > + iio_device_release_direct(indio_dev); > + return ret; > +} > + > +#define AD4052_EXT_INFO(grade) \ > +static struct iio_chan_spec_ext_info grade##_ext_info[] = { \ > + IIO_ENUM("sample_rate", IIO_SHARED_BY_ALL, &grade##_sample_rate_enum), \ > + IIO_ENUM_AVAILABLE("sample_rate", IIO_SHARED_BY_ALL, &grade##_sample_rate_enum),\ > + {} \ { } preferred slightly. > +} > +static int ad4052_get_oversampling_ratio(struct ad4052_state *st, > + unsigned int *val) > +{ > + int ret; > + > + if (st->mode == AD4052_SAMPLE_MODE) { > + *val = 0; Probably = 1 to reflect no oversampling. IIRC the attribute allows either but to me at least a default of 1 is more logical. > + return 0; > + } > + > + ret = regmap_read(st->regmap, AD4052_REG_AVG_CONFIG, val); > + if (ret) > + return ret; > + > + *val = BIT(*val + 1); > + > + return 0; > +} > + > +static int ad4052_assert(struct ad4052_state *st) Slighly odd name. check_ids or something like that. > +{ > + int ret; > + u16 val; > + > + ret = regmap_bulk_read(st->regmap, AD4052_REG_PROD_ID_1, &st->d16, 2); sizeof(st->d16) here and in similar places. > + if (ret) > + return ret; > + > + val = be16_to_cpu(st->d16); > + if (val != st->chip->prod_id) > + return -ENODEV; Should not be treated as a failure as that breaks the future use of fallback compatible values in DT (support new hardware on old kernel) Instead just print a message saying it didn't match and carry on as if it did. > + > + ret = regmap_bulk_read(st->regmap, AD4052_REG_VENDOR_H, &st->d16, 2); > + if (ret) > + return ret; > + > + val = be16_to_cpu(st->d16); > + if (val != AD4052_SPI_VENDOR) > + return -ENODEV; > + > + return 0; > +} > + > +static int ad4052_set_operation_mode(struct ad4052_state *st, enum ad4052_operation_mode mode) > +{ > + u8 val = st->data_format | mode; Maybe regmap_update_bits so we don't have to store st->data_format if that bit has already been written. > + int ret; > + > + ret = regmap_write(st->regmap, AD4052_REG_ADC_MODES, val); > + if (ret) > + return ret; > + > + val = BIT(0); This should have some sort of define and then use that inline in the regmap_write() call. > + return regmap_write(st->regmap, AD4052_REG_MODE_SET, val); > +} > + > +static int ad4052_set_non_defaults(struct iio_dev *indio_dev, i kind of get where you are coming from with the 'non defaults' but we are setting software driven defaults here. Maybe just rename as ad4052_setup() or something similarly vague. > + struct iio_chan_spec const *chan) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + const struct iio_scan_type *scan_type; > + > + scan_type = iio_get_current_scan_type(indio_dev, chan); > + > + u8 val = FIELD_PREP(AD4052_GP_MODE_MSK(0), AD4052_GP_INTR) | > + FIELD_PREP(AD4052_GP_MODE_MSK(1), AD4052_GP_DRDY); > + int ret; > + > + ret = regmap_update_bits(st->regmap, AD4052_REG_GP_CONFIG, > + AD4052_GP_MODE_MSK(1) | AD4052_GP_MODE_MSK(0), > + val); > + if (ret) > + return ret; > + > + val = FIELD_PREP(AD4052_INTR_EN_MSK(0), (AD4052_INTR_EN_EITHER)) | > + FIELD_PREP(AD4052_INTR_EN_MSK(1), (AD4052_INTR_EN_NEITHER)); > + > + ret = regmap_update_bits(st->regmap, AD4052_REG_INTR_CONFIG, > + AD4052_INTR_EN_MSK(0) | AD4052_INTR_EN_MSK(1), > + val); > + if (ret) > + return ret; > + > + val = 0; > + if (scan_type->sign == 's') > + val |= AD4052_DATA_FORMAT; > + > + st->data_format = val; > + > + if (st->chip->grade == AD4052_500KSPS) { > + ret = regmap_write(st->regmap, AD4052_REG_TIMER_CONFIG, > + FIELD_PREP(AD4052_FS_MASK, AD4052_300KSPS)); > + if (ret) > + return ret; > + } > + > + return regmap_write(st->regmap, AD4052_REG_ADC_MODES, val); > +} > + > +static int ad4052_request_irq(struct iio_dev *indio_dev) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + struct device *dev = &st->spi->dev; > + int ret = 0; > + > + ret = fwnode_irq_get(dev_fwnode(&st->spi->dev), 0); As per the binding review, use named variant as we should not be controlling the order, but rather specifying which is which in the dt-binding. > + if (ret <= 0) > + return ret ? ret : -EINVAL; > + > + ret = devm_request_threaded_irq(dev, > + ret, NULL, ad4052_irq_handler_thresh, odd wrap. Take each line up to 80 chars before wrapping to next one. > + IRQF_TRIGGER_RISING | IRQF_ONESHOT, Direction should come from firmware, not be specified here. There might be an inverter in the path. That used to be a common cheap way of doing level conversion for interrupt lines and it is handled by flipping the sense of the interrupt in the dts. > + indio_dev->name, indio_dev); > + if (ret) > + return ret; > + > + ret = fwnode_irq_get(dev_fwnode(&st->spi->dev), 1); > + if (ret <= 0) > + return ret ? ret : -EINVAL; > + > + st->gp1_irq = ret; > + ret = devm_request_threaded_irq(dev, > + ret, NULL, ad4052_irq_handler_drdy, > + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, > + indio_dev->name, st); return devm_request_thread_irq. > + return ret; > +} > + > +static const int ad4052_oversampling_avail[] = { > + 0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096 Always a trailing comma unless it is some form of terminator. Oversampling ratio of 0 is a bit strange. That should probably be 1 to reflect 1 sample per reading output (or no oversampling). > +}; > + > +static ssize_t ad4052_set_sampling_freq(struct ad4052_state *st, unsigned int val) > +{ > + int ret; > + > + if (AD4052_CHECK_RATE(st->chip->grade, val)) > + return -EINVAL; > + > + ret = __ad4052_set_sampling_freq(st, val); > + > + return ret; return __ad4052_set_sampling_freq(st, val); > +} > +static int ad4052_write_event_config(struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan, > + enum iio_event_type type, > + enum iio_event_direction dir, > + bool state) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + int ret = -EBUSY; > + > + if (!iio_device_claim_direct(indio_dev)) > + return -EBUSY; > + > + if (st->wait_event == state) > + goto out_release; > + > + if (state) { > + ret = pm_runtime_resume_and_get(&st->spi->dev); > + if (ret) > + goto out_release; > + > + ret = ad4052_set_operation_mode(st, AD4052_MONITOR_MODE); > + if (ret) > + goto out_err_suspend; Given the error handling is different in the two paths, I'd split this into two helpers - one each for enable and disable. Probably take the direct claim around where they are called. > + } else { > + pm_runtime_mark_last_busy(&st->spi->dev); > + pm_runtime_put_autosuspend(&st->spi->dev); > + > + ret = ad4052_exit_command(st); > + } > + st->wait_event = state; > + iio_device_release_direct(indio_dev); > + return ret; > + > +out_err_suspend: > + pm_runtime_mark_last_busy(&st->spi->dev); > + pm_runtime_put_autosuspend(&st->spi->dev); > + > +out_release: > + iio_device_release_direct(indio_dev); > + return ret; > +} > + > +static int ad4052_read_event_value(struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan, > + enum iio_event_type type, > + enum iio_event_direction dir, > + enum iio_event_info info, int *val, > + int *val2) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + u8 reg, size = 1; > + int ret; > + > + if (!ad4052_iio_device_claim_direct(indio_dev, st)) > + return -EBUSY; > + > + switch (info) { > + case IIO_EV_INFO_VALUE: > + if (dir == IIO_EV_DIR_RISING) > + reg = AD4052_REG_MAX_LIMIT; > + else > + reg = AD4052_REG_MIN_LIMIT; > + size++; As below. Seems to me better to just set size to 2 here. > + break; > + case IIO_EV_INFO_HYSTERESIS: > + if (dir == IIO_EV_DIR_RISING) > + reg = AD4052_REG_MAX_HYST; > + else > + reg = AD4052_REG_MIN_HYST; > + break; > + default: > + iio_device_release_direct(indio_dev); > + return -EINVAL; Maybe use an error block and goto. You could factor out the stuff under the direct claim as an alternative path to simpler code. > + } > + > + ret = regmap_bulk_read(st->regmap, reg, &st->d32, size); > + if (ret) { > + iio_device_release_direct(indio_dev); > + return ret; > + } > + > + if (reg == AD4052_REG_MAX_LIMIT || reg == AD4052_REG_MIN_LIMIT) { > + *val = be16_to_cpu(st->d16); > + if (st->data_format & AD4052_DATA_FORMAT) > + *val = sign_extend32(*val, 11); > + } else { > + *val = st->d32; > + } > + > + iio_device_release_direct(indio_dev); > + return IIO_VAL_INT; > +} > + > +static int ad4052_write_event_value(struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan, > + enum iio_event_type type, > + enum iio_event_direction dir, > + enum iio_event_info info, int val, > + int val2) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + int ret = -EINVAL; > + u8 reg, size = 1; > + > + if (!ad4052_iio_device_claim_direct(indio_dev, st)) > + return -EBUSY; > + > + st->d16 = cpu_to_be16(val); > + > + switch (type) { > + case IIO_EV_TYPE_THRESH: > + switch (info) { > + case IIO_EV_INFO_VALUE: > + if (st->data_format & AD4052_DATA_FORMAT) { > + if (val > 2047 || val < -2048) > + goto out_release; > + } else if (val > 4095 || val < 0) { > + goto out_release; > + } > + if (dir == IIO_EV_DIR_RISING) > + reg = AD4052_REG_MAX_LIMIT; > + else > + reg = AD4052_REG_MIN_LIMIT; > + size++; Set size directly to 2 perhaps. I'm not really understanding why the increment scheme makes more sense. > + break; > + case IIO_EV_INFO_HYSTERESIS: > + if (val & BIT(7)) > + goto out_release; > + if (dir == IIO_EV_DIR_RISING) > + reg = AD4052_REG_MAX_HYST; > + else > + reg = AD4052_REG_MIN_HYST; > + st->d16 >>= 8; > + break; > + default: > + goto out_release; > + } > + break; > + default: > + goto out_release; > + } > + > + ret = regmap_bulk_write(st->regmap, reg, &st->d16, size); > + > +out_release: > + iio_device_release_direct(indio_dev); > + return ret; > +} > + > +static int ad4052_buffer_preenable(struct iio_dev *indio_dev) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + struct spi_offload_trigger_config config = { > + .type = SPI_OFFLOAD_TRIGGER_PERIODIC, > + .periodic = { > + .frequency_hz = st->offload_trigger_hz, > + }, > + }; > + int ret; > + > + if (st->wait_event) > + return -EBUSY; > + > + ret = pm_runtime_resume_and_get(&st->spi->dev); > + if (ret) > + return ret; > + > + ret = ad4052_set_operation_mode(st, st->mode); > + if (ret) > + goto out_error; > + > + ret = ad4052_update_xfer_offload(indio_dev, indio_dev->channels); > + if (ret) > + goto out_error; > + > + disable_irq(st->gp1_irq); Add a comment on why. > + > + ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, > + &config); > + if (ret) > + goto out_offload_error; > + > + return 0; > + > +out_offload_error: > + enable_irq(st->gp1_irq); > +out_error: > + pm_runtime_mark_last_busy(&st->spi->dev); > + pm_runtime_put_autosuspend(&st->spi->dev); > + > + return ret; > +} > +static int ad4052_get_current_scan_type(const struct iio_dev *indio_dev, > + const struct iio_chan_spec *chan) > +{ > + struct ad4052_state *st = iio_priv(indio_dev); > + > + /* > + * REVISIT: the supported offload has a fixed length of 32-bits > + * to fit the 24-bits oversampled case, requiring the additional > + * offload scan types. > + */ That's an additional feature I think. We don't need to have a comment about things we haven't done in the driver. > + if (iio_buffer_enabled(indio_dev)) > + return st->mode == AD4052_BURST_AVERAGING_MODE ? > + AD4052_SCAN_TYPE_OFFLOAD_BURST_AVG : > + AD4052_SCAN_TYPE_OFFLOAD_SAMPLE; > + > + return st->mode == AD4052_BURST_AVERAGING_MODE ? > + AD4052_SCAN_TYPE_BURST_AVG : > + AD4052_SCAN_TYPE_SAMPLE; > +} > +static int ad4052_probe(struct spi_device *spi) > +{ > + const struct ad4052_chip_info *chip; > + struct device *dev = &spi->dev; > + struct iio_dev *indio_dev; > + struct ad4052_state *st; > + int ret; > + u8 buf; > + > + chip = spi_get_device_match_data(spi); > + if (!chip) > + return dev_err_probe(dev, -ENODEV, > + "Could not find chip info data\n"); > + > + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); > + if (!indio_dev) > + return -ENOMEM; > + > + st = iio_priv(indio_dev); > + st->spi = spi; > + spi_set_drvdata(spi, st); > + init_completion(&st->completion); > + > + st->regmap = devm_regmap_init_spi(spi, &ad4052_regmap_config); > + if (IS_ERR(st->regmap)) > + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), Use dev instead of spi->dev > + "Failed to initialize regmap\n"); > + > + st->mode = AD4052_SAMPLE_MODE; > + st->wait_event = false; > + st->chip = chip; > + > + st->cnv_gp = devm_gpiod_get_optional(dev, "cnv", > + GPIOD_OUT_LOW); wrap to 80 chars - so don't wrap the above. > + if (IS_ERR(st->cnv_gp)) > + return dev_err_probe(dev, PTR_ERR(st->cnv_gp), > + "Failed to get cnv gpio\n"); > + > + indio_dev->modes = INDIO_BUFFER_HARDWARE | INDIO_DIRECT_MODE; > + indio_dev->num_channels = 1; > + indio_dev->info = &ad4052_info; > + indio_dev->name = chip->name; > + > + st->offload = devm_spi_offload_get(dev, spi, &ad4052_offload_config); > + ret = PTR_ERR_OR_ZERO(st->offload); Use IS_ERR() to detect error and PTR_ERR() to get it if needed (will end up calling PTR_ERR() twice but similar anyway. > + if (ret && ret != -ENODEV) > + return dev_err_probe(dev, ret, "Failed to get offload\n"); > + > + if (ret == -ENODEV) { > + st->offload_trigger = NULL; > + indio_dev->channels = chip->channels; > + } else { > + indio_dev->channels = chip->offload_channels; > + ret = ad4052_request_offload(indio_dev); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to configure offload\n"); > + } > + > + st->xfer.rx_buf = &st->d32; > + > + ret = ad4052_soft_reset(st); > + if (ret) > + return dev_err_probe(dev, ret, > + "AD4052 failed to soft reset\n"); No need to wrap as fairly sure that's under 80 chars anyway. > + > + ret = ad4052_assert(st); > + if (ret) > + return dev_err_probe(dev, ret, > + "AD4052 fields assertions failed\n"); > + > + ret = ad4052_set_non_defaults(indio_dev, indio_dev->channels); > + if (ret) > + return ret; > + > + buf = AD4052_DEVICE_RESET; Pass directly into regmap_write() > + ret = regmap_write(st->regmap, AD4052_REG_DEVICE_STATUS, buf); > + if (ret) > + return ret; > + > + ret = ad4052_request_irq(indio_dev); > + if (ret) > + return ret; > + > + ad4052_update_xfer_raw(indio_dev, indio_dev->channels); > + > + pm_runtime_set_autosuspend_delay(dev, 1000); > + pm_runtime_use_autosuspend(dev); These autosuspend things are normally done after enabling runtime pm. If nothing else that keeps the devm cleanup as being in opposite order of what is set up here. https://elixir.bootlin.com/linux/v6.13.5/source/drivers/base/power/runtime.c#L1548 > + pm_runtime_set_active(dev); > + ret = devm_pm_runtime_enable(dev); > + if (ret) > + return dev_err_probe(dev, ret, > + "Failed to enable pm_runtime\n"); > + > + return devm_iio_device_register(dev, indio_dev); > +} > + > +static int ad4052_runtime_suspend(struct device *dev) > +{ > + u8 val = FIELD_PREP(AD4052_POWER_MODE_MSK, AD4052_LOW_POWER_MODE); Put that inline and no need for local variable val. > + struct ad4052_state *st = dev_get_drvdata(dev); > + > + return regmap_write(st->regmap, AD4052_REG_DEVICE_CONFIG, val); > +} > + > +static int ad4052_runtime_resume(struct device *dev) > +{ > + struct ad4052_state *st = dev_get_drvdata(dev); > + u8 val = FIELD_PREP(AD4052_POWER_MODE_MSK, 0); Put that inline - no real point in the local variable. > + int ret; > + > + ret = regmap_write(st->regmap, AD4052_REG_DEVICE_CONFIG, val); ret = regmap_write(st->regmap, AD4052_REG_DEVICE_CONFIG, FIELD_PREP(AD4052_POWER_MODE_MSK, 0)); > + if (ret) > + return ret; > + > + fsleep(2000); Sleeps like this should ideally have a spec reference as a comment to justify why that value is chosen. > + return 0; > +} > + > +static const struct dev_pm_ops ad4052_pm_ops = { > + RUNTIME_PM_OPS(ad4052_runtime_suspend, ad4052_runtime_resume, NULL) Can you allow this to be used for suspend and resume as well? e.g. DEFINE_RUNTIME_DEV_PM_OPS() It is a rare case where that isn't safe to do even if there might be deeper sleep states available that would be even better. > +}; > + > +static const struct spi_device_id ad4052_id_table[] = { > + {"ad4050", (kernel_ulong_t)&ad4050_chip_info }, > + {"ad4052", (kernel_ulong_t)&ad4052_chip_info }, > + {"ad4056", (kernel_ulong_t)&ad4056_chip_info }, > + {"ad4058", (kernel_ulong_t)&ad4058_chip_info }, > + {} > +}; > +MODULE_DEVICE_TABLE(spi, ad4052_id_table); > + > +static const struct of_device_id ad4052_of_match[] = { > + { .compatible = "adi,ad4050", .data = &ad4050_chip_info }, > + { .compatible = "adi,ad4052", .data = &ad4052_chip_info }, > + { .compatible = "adi,ad4056", .data = &ad4056_chip_info }, > + { .compatible = "adi,ad4058", .data = &ad4058_chip_info }, > + {} Trivial but I'm slowly trying to standardize formatting of these tables in IIO and I randomly decided to go with { } Please use that for terminating entries in this new driver. > +}; > +MODULE_DEVICE_TABLE(of, ad4052_of_match);
Le 06/03/2025 à 15:03, Jorge Marques a écrit : > The AD4052/AD4058/AD4050/AD4056 are versatile, 16-bit/12-bit, > successive approximation register (SAR) analog-to-digital converter (ADC) > that enables low-power, high-density data acquisition solutions without > sacrificing precision. ... > +#define AD4052_CHAN(bits, grade) { \ > + .type = IIO_VOLTAGE, \ > + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ > + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ > + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ Nitpick: Unneeded extra space before BIT > + .indexed = 1, \ > + .channel = 0, \ > + .event_spec = ad4052_events, \ > + .num_event_specs = ARRAY_SIZE(ad4052_events), \ > + .has_ext_scan_type = 1, \ > + .ext_scan_type = ad4052_scan_type_##bits##_s, \ > + .num_ext_scan_type = ARRAY_SIZE(ad4052_scan_type_##bits##_s), \ > + .ext_info = grade##_ext_info, \ > +} > + > +#define AD4052_OFFLOAD_CHAN(bits, grade) { \ > + .type = IIO_VOLTAGE, \ > + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ > + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ > + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ > + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ Nitpick: Unneeded extra space before BIT > + .indexed = 1, \ > + .channel = 0, \ > + .event_spec = ad4052_events, \ > + .num_event_specs = ARRAY_SIZE(ad4052_events), \ > + .has_ext_scan_type = 1, \ > + .ext_scan_type = ad4052_scan_type_##bits##_s, \ > + .num_ext_scan_type = ARRAY_SIZE(ad4052_scan_type_##bits##_s), \ > + .ext_info = grade##_ext_info, \ > +} ... > +static int ad4052_probe(struct spi_device *spi) > +{ > + const struct ad4052_chip_info *chip; > + struct device *dev = &spi->dev; > + struct iio_dev *indio_dev; > + struct ad4052_state *st; > + int ret; > + u8 buf; > + > + chip = spi_get_device_match_data(spi); > + if (!chip) > + return dev_err_probe(dev, -ENODEV, > + "Could not find chip info data\n"); > + > + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); > + if (!indio_dev) > + return -ENOMEM; > + > + st = iio_priv(indio_dev); > + st->spi = spi; > + spi_set_drvdata(spi, st); > + init_completion(&st->completion); > + > + st->regmap = devm_regmap_init_spi(spi, &ad4052_regmap_config); > + if (IS_ERR(st->regmap)) > + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), Nitpick: Unneeded extra space before PTR_ERR > + "Failed to initialize regmap\n"); > + > + st->mode = AD4052_SAMPLE_MODE; > + st->wait_event = false; > + st->chip = chip; ... CJ
Hi Jonathan thank you for the review, comments excluded in the reply are agreed and applied. > > --- a/drivers/iio/adc/Kconfig > > +++ b/drivers/iio/adc/Kconfig > > To compile this driver as a module, choose M here: the module will be > > called ad4130. > > > > +config AD4052 > Aim for alphanumeric order so this should at least be before AD4130 Ups, I got tricked during cherry-pick. > > +#define AD4052_MIN_FLAG BIT(2) > > +#define AD4052_EVENT_CLEAR (AD4052_THRESH_OVERRUN | AD4052_MAX_FLAG | AD4052_MIN_FLAG) > Wrap the define with \ to break the line. Deadcode... removed. > > +}; > > + > > +static const char *const ad4052_sample_rates[] = { > > + "2000000", "1000000", "300000", "100000", "33300", > > + "10000", "3000", "500", "333", "250", "200", > > + "166", "140", "124", "111", > Not sure why this can't be done with read_avail and the values above. Since it is the internal device sample rate, it is an extended device attribute. The channel IIO_SAMPLING_FREQUENCY is used for the sampling frequency during buffer readings. The macro IIO_ENUM_AVAILABLE is used to reduce redundancy. The previous integer declaration was unused since the char array index is used as the register r/w value. > > +}; > > + > > +static int ad4052_iio_device_claim_direct(struct iio_dev *indio_dev, > > + struct ad4052_state *st) > > +{ > > + if (!iio_device_claim_direct(indio_dev)) > > + return false; > > This might stretch sparses ability to keep track or __acquire / __release. > Make sure to check that with a C=1 build. If the cond_acquires > stuff is merged into sparse, this may need a revisit for markings. You are right! I also did further fixes caught by sparse. > > +{ > > + int ret; > > + > > + if (st->mode == AD4052_SAMPLE_MODE) { > > + *val = 0; > > Probably = 1 to reflect no oversampling. > IIRC the attribute allows either but to me at least a default of 1 > is more logical. Agreed, 1 is now the only no oversampling value. > > +} > > + > > +static int ad4052_assert(struct ad4052_state *st) > Slighly odd name. check_ids or something like that. > Went with 'check_ids'. > > + > > + val = be16_to_cpu(st->d16); > > + if (val != st->chip->prod_id) > > + return -ENODEV; > > Should not be treated as a failure as that breaks the future use of > fallback compatible values in DT (support new hardware on old kernel) > Instead just print a message saying it didn't match and carry on as if it did. Noted, added: "Production ID x%x does not match known values", val); > > +{ > > + struct ad4052_state *st = iio_priv(indio_dev); > > + struct device *dev = &st->spi->dev; > > + int ret = 0; > > + > > + ret = fwnode_irq_get(dev_fwnode(&st->spi->dev), 0); > > As per the binding review, use named variant as we should > not be controlling the order, but rather specifying which > is which in the dt-binding. Makes more sense indeed. > > + IRQF_TRIGGER_RISING | IRQF_ONESHOT, > > Direction should come from firmware, not be specified here. > There might be an inverter in the path. That used to be a common cheap > way of doing level conversion for interrupt lines and it is handled by > flipping the sense of the interrupt in the dts. > Agreed, defined the level flags as 0, and kept IRQF_ONESHOT the irq flag, to dismiss the threaded IRQ with NULL handler needs to be oneshot. > > +static int ad4052_write_event_config(struct iio_dev *indio_dev, > > + const struct iio_chan_spec *chan, > > + enum iio_event_type type, > > + enum iio_event_direction dir, > > + bool state) > > +{ > > + struct ad4052_state *st = iio_priv(indio_dev); > > + int ret = -EBUSY; > > + > > + if (!iio_device_claim_direct(indio_dev)) > > + return -EBUSY; > > + > > + if (st->wait_event == state) > > + goto out_release; > > + > > + if (state) { > > + ret = pm_runtime_resume_and_get(&st->spi->dev); > > + if (ret) > > + goto out_release; > > + > > + ret = ad4052_set_operation_mode(st, AD4052_MONITOR_MODE); > > + if (ret) > > + goto out_err_suspend; > Given the error handling is different in the two paths, I'd > split this into two helpers - one each for enable and disable. > Probably take the direct claim around where they are called. Yes, that will make it easier to follow. > > + > > + ret = ad4052_update_xfer_offload(indio_dev, indio_dev->channels); > > + if (ret) > > + goto out_error; > > + > > + disable_irq(st->gp1_irq); > > Add a comment on why. Added /* SPI Offload handles the data ready irq */ > > + struct ad4052_state *st = iio_priv(indio_dev); > > + > > + /* > > + * REVISIT: the supported offload has a fixed length of 32-bits > > + * to fit the 24-bits oversampled case, requiring the additional > > + * offload scan types. > > + */ > > That's an additional feature I think. We don't need to have a comment > about things we haven't done in the driver. Removed comment. > > + if (IS_ERR(st->cnv_gp)) > > + return dev_err_probe(dev, PTR_ERR(st->cnv_gp), > > + "Failed to get cnv gpio\n"); > > + > > + indio_dev->modes = INDIO_BUFFER_HARDWARE | INDIO_DIRECT_MODE; > > + indio_dev->num_channels = 1; > > + indio_dev->info = &ad4052_info; > > + indio_dev->name = chip->name; > > + > > + st->offload = devm_spi_offload_get(dev, spi, &ad4052_offload_config); > > + ret = PTR_ERR_OR_ZERO(st->offload); > > Use IS_ERR() to detect error and PTR_ERR() to get it if needed (will > end up calling PTR_ERR() twice but similar anyway. Ok. > > + ret = regmap_write(st->regmap, AD4052_REG_DEVICE_STATUS, buf); > > + if (ret) > > + return ret; > > + > > + ret = ad4052_request_irq(indio_dev); > > + if (ret) > > + return ret; > > + > > + ad4052_update_xfer_raw(indio_dev, indio_dev->channels); > > + > > + pm_runtime_set_autosuspend_delay(dev, 1000); > > + pm_runtime_use_autosuspend(dev); > > These autosuspend things are normally done after enabling runtime pm. > If nothing else that keeps the devm cleanup as being in opposite > order of what is set up here. > https://elixir.bootlin.com/linux/v6.13.5/source/drivers/base/power/runtime.c#L1548 Makes sense. > > + if (ret) > > + return ret; > > + > > + fsleep(2000); > > Sleeps like this should ideally have a spec reference as a comment to > justify why that value is chosen. > This sleep is not needed since there is no timing specification in the datasheet, removed. > > + return 0; > > +} > > + > > +static const struct dev_pm_ops ad4052_pm_ops = { > > + RUNTIME_PM_OPS(ad4052_runtime_suspend, ad4052_runtime_resume, NULL) > Can you allow this to be used for suspend and resume as well? e.g. > DEFINE_RUNTIME_DEV_PM_OPS() > > It is a rare case where that isn't safe to do even if there might be > deeper sleep states available that would be even better. Yes. > > + {} > Trivial but I'm slowly trying to standardize formatting of these tables > in IIO and I randomly decided to go with > { } > Please use that for terminating entries in this new driver. Done on all instances. I will wait further reviews before resubmitting the patch If useful for other reviewers, my current head is at https://github.com/analogdevicesinc/linux/tree/staging/ad4052 Jorge
Applied suggestions, thanks! Jorge
diff --git a/MAINTAINERS b/MAINTAINERS index 312b2cf94b8f06298b1cbe5975ee32e2cf9a74d8..275e2bace4731d37a3ef8eab173d11514e482e72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1323,6 +1323,7 @@ S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4052.yaml F: Documentation/iio/ad4052.rst +F: drivers/iio/adc/ad4052.c ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav <cosmin.tanislav@analog.com> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 27413516216cb3f83cf1d995b9ffc22bf01776a4..f518dadbdd3a6b0543d0b78206fcbc203898454c 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -62,6 +62,20 @@ config AD4130 To compile this driver as a module, choose M here: the module will be called ad4130. +config AD4052 + tristate "Analog Devices AD4052 Driver" + depends on SPI + select SPI_OFFLOAD + select IIO_BUFFER + select IIO_BUFFER_DMAENGINE + select REGMAP_SPI + help + Say yes here to build support for Analog Devices AD4052 SPI analog + to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4052. + config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 9f26d5eca8225e28f308b3db437e25eb45b41a3c..412e35dfeb9be244c47e384d3abb67cef943a0f0 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o obj-$(CONFIG_AD4000) += ad4000.o obj-$(CONFIG_AD4030) += ad4030.o obj-$(CONFIG_AD4130) += ad4130.o +obj-$(CONFIG_AD4052) += ad4052.o obj-$(CONFIG_AD4695) += ad4695.o obj-$(CONFIG_AD4851) += ad4851.o obj-$(CONFIG_AD7091R) += ad7091r-base.o diff --git a/drivers/iio/adc/ad4052.c b/drivers/iio/adc/ad4052.c new file mode 100644 index 0000000000000000000000000000000000000000..29452963fb15ab1b11e3a2fc59c34a2579f25910 --- /dev/null +++ b/drivers/iio/adc/ad4052.c @@ -0,0 +1,1289 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD4052 SPI ADC driver + * + * Copyright 2025 Analog Devices Inc. + */ +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/iio/buffer.h> +#include <linux/iio/buffer-dmaengine.h> +#include <linux/iio/events.h> +#include <linux/iio/iio.h> +#include <linux/interrupt.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/offload/consumer.h> + +#define AD4052_REG_INTERFACE_CONFIG_A 0x00 +#define AD4052_REG_DEVICE_CONFIG 0x02 +#define AD4052_REG_PROD_ID_1 0x05 +#define AD4052_REG_DEVICE_GRADE 0x06 +#define AD4052_REG_SCRATCH_PAD 0x0A +#define AD4052_REG_VENDOR_H 0x0D +#define AD4052_REG_STREAM_MODE 0x0E +#define AD4052_REG_INTERFACE_STATUS 0x11 +#define AD4052_REG_MODE_SET 0x20 +#define AD4052_REG_ADC_MODES 0x21 +#define AD4052_REG_AVG_CONFIG 0x23 +#define AD4052_REG_GP_CONFIG 0x24 +#define AD4052_REG_INTR_CONFIG 0x25 +#define AD4052_REG_TIMER_CONFIG 0x27 +#define AD4052_REG_MAX_LIMIT 0x29 +#define AD4052_REG_MIN_LIMIT 0x2B +#define AD4052_REG_MAX_HYST 0x2C +#define AD4052_REG_MIN_HYST 0x2D +#define AD4052_REG_MON_VAL 0x2F +#define AD4052_REG_FUSE_CRC 0x40 +#define AD4052_REG_DEVICE_STATUS 0x41 +#define AD4052_REG_MIN_SAMPLE 0x45 +#define AD4052_MAX_REG 0x45 +/* GP_CONFIG */ +#define AD4052_GP_MODE_MSK(x) (GENMASK(2, 0) << (x) * 4) +/* INTR_CONFIG */ +#define AD4052_INTR_EN_MSK(x) (GENMASK(1, 0) << (x) * 4) +/* ADC_MODES */ +#define AD4052_DATA_FORMAT BIT(7) +/* DEVICE_CONFIG */ +#define AD4052_POWER_MODE_MSK GENMASK(1, 0) +#define AD4052_LOW_POWER_MODE 3 +/* DEVICE_STATUS */ +#define AD4052_DEVICE_RESET BIT(6) +#define AD4052_THRESH_OVERRUN BIT(4) +#define AD4052_MAX_FLAG BIT(3) +#define AD4052_MIN_FLAG BIT(2) +#define AD4052_EVENT_CLEAR (AD4052_THRESH_OVERRUN | AD4052_MAX_FLAG | AD4052_MIN_FLAG) +/* TIMER_CONFIG */ +#define AD4052_FS_MASK GENMASK(7, 4) +#define AD4052_300KSPS 0x2 + +#define AD4052_SPI_VENDOR 0x0456 + +#define AD4050_MAX_AVG 0x7 +#define AD4052_MAX_AVG 0xB +#define AD4052_CHECK_OVERSAMPLING(x, y) ({typeof(y) y_ = (y); \ + ((y_) < 0 || (y_) > BIT((x) + 1)); }) +#define AD4052_MAX_RATE(x) ((x) == AD4052_500KSPS ? 500000 : 2000000) +#define AD4052_CHECK_RATE(x, y) ({typeof(y) y_ = (y); \ + ((y_) > AD4052_MAX_RATE(x) || (y_) <= 0); }) +#define AD4052_FS_OFFSET(g) ((g) == AD4052_500KSPS ? 2 : 0) +#define AD4052_FS(g) (&ad4052_sample_rates[AD4052_FS_OFFSET(g)]) +#define AD4052_FS_LEN(g) (ARRAY_SIZE(ad4052_sample_rates) - (AD4052_FS_OFFSET(g))) + +enum ad4052_grade { + AD4052_2MSPS, + AD4052_500KSPS, +}; + +enum ad4052_operation_mode { + AD4052_SAMPLE_MODE = 0, + AD4052_BURST_AVERAGING_MODE = 1, + AD4052_MONITOR_MODE = 3, +}; + +enum ad4052_gp_mode { + AD4052_GP_DISABLED, + AD4052_GP_INTR, + AD4052_GP_DRDY, +}; + +enum ad4052_interrupt_en { + AD4052_INTR_EN_NEITHER, + AD4052_INTR_EN_MIN, + AD4052_INTR_EN_MAX, + AD4052_INTR_EN_EITHER, +}; + +struct ad4052_chip_info { + const struct iio_chan_spec channels[1]; + const struct iio_chan_spec offload_channels[1]; + const char *name; + u16 prod_id; + u8 max_avg; + u8 grade; +}; + +enum { + AD4052_SCAN_TYPE_SAMPLE, + AD4052_SCAN_TYPE_BURST_AVG, + AD4052_SCAN_TYPE_OFFLOAD_SAMPLE, + AD4052_SCAN_TYPE_OFFLOAD_BURST_AVG, +}; + +static const struct iio_scan_type ad4052_scan_type_12_s[] = { + [AD4052_SCAN_TYPE_SAMPLE] = { + .sign = 's', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_BURST_AVG] = { + .sign = 's', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_OFFLOAD_SAMPLE] = { + .sign = 's', + .realbits = 16, + .storagebits = 32, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_OFFLOAD_BURST_AVG] = { + .sign = 's', + .realbits = 16, + .storagebits = 32, + .endianness = IIO_CPU, + }, +}; + +static const struct iio_scan_type ad4052_scan_type_16_s[] = { + [AD4052_SCAN_TYPE_SAMPLE] = { + .sign = 's', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_BURST_AVG] = { + .sign = 's', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_OFFLOAD_SAMPLE] = { + .sign = 's', + .realbits = 16, + .storagebits = 32, + .endianness = IIO_CPU, + }, + [AD4052_SCAN_TYPE_OFFLOAD_BURST_AVG] = { + .sign = 's', + .realbits = 24, + .storagebits = 32, + .endianness = IIO_CPU, + }, +}; + +struct ad4052_state { + const struct ad4052_bus_ops *ops; + const struct ad4052_chip_info *chip; + enum ad4052_operation_mode mode; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + unsigned long offload_trigger_hz; + struct spi_device *spi; + struct spi_transfer offload_xfer; + struct spi_message offload_msg; + struct spi_transfer xfer; + struct spi_message msg; + struct gpio_desc *cnv_gp; + struct completion completion; + struct regmap *regmap; + bool wait_event; + int gp1_irq; + u8 data_format; + union { + __be16 d16; + __be32 d32; + } __aligned(IIO_DMA_MINALIGN); + u8 buf_reset_pattern[18]; +}; + +static const struct regmap_range ad4052_regmap_rd_ranges[] = { + regmap_reg_range(AD4052_REG_INTERFACE_CONFIG_A, AD4052_REG_DEVICE_GRADE), + regmap_reg_range(AD4052_REG_SCRATCH_PAD, AD4052_REG_INTERFACE_STATUS), + regmap_reg_range(AD4052_REG_MODE_SET, AD4052_REG_MON_VAL), + regmap_reg_range(AD4052_REG_FUSE_CRC, AD4052_REG_MIN_SAMPLE), +}; + +static const struct regmap_access_table ad4052_regmap_rd_table = { + .yes_ranges = ad4052_regmap_rd_ranges, + .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_rd_ranges), +}; + +static const struct regmap_range ad4052_regmap_wr_ranges[] = { + regmap_reg_range(AD4052_REG_INTERFACE_CONFIG_A, AD4052_REG_DEVICE_CONFIG), + regmap_reg_range(AD4052_REG_SCRATCH_PAD, AD4052_REG_SCRATCH_PAD), + regmap_reg_range(AD4052_REG_STREAM_MODE, AD4052_REG_INTERFACE_STATUS), + regmap_reg_range(AD4052_REG_MODE_SET, AD4052_REG_MON_VAL), + regmap_reg_range(AD4052_REG_FUSE_CRC, AD4052_REG_DEVICE_STATUS), +}; + +static const struct regmap_access_table ad4052_regmap_wr_table = { + .yes_ranges = ad4052_regmap_wr_ranges, + .n_yes_ranges = ARRAY_SIZE(ad4052_regmap_wr_ranges), +}; + +static const struct iio_event_spec ad4052_events[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE) + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_HYSTERESIS) + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_HYSTERESIS) + } +}; + +static const int ad4052_sample_rate_avail[] = { + 2000000, 1000000, 300000, 100000, 33300, + 10000, 3000, 500, 333, 250, 200, + 166, 140, 125, 111 +}; + +static const char *const ad4052_sample_rates[] = { + "2000000", "1000000", "300000", "100000", "33300", + "10000", "3000", "500", "333", "250", "200", + "166", "140", "124", "111", +}; + +static int ad4052_iio_device_claim_direct(struct iio_dev *indio_dev, + struct ad4052_state *st) +{ + if (!iio_device_claim_direct(indio_dev)) + return false; + + /** + * If the device is in monitor mode, no register access is allowed, + * since it would put the device back in configuration mode. + */ + if (st->wait_event) { + iio_device_release_direct(indio_dev); + return false; + } + return true; +} + +static int ad4052_sample_rate_get(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret, val; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + ret = regmap_read(st->regmap, AD4052_REG_TIMER_CONFIG, &val); + val = FIELD_GET(AD4052_FS_MASK, val); + + iio_device_release_direct(indio_dev); + return ret ? ret : val - AD4052_FS_OFFSET(st->chip->grade); +} + +static int ad4052_sample_rate_set(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + val += AD4052_FS_OFFSET(st->chip->grade); + val = FIELD_PREP(AD4052_FS_MASK, val); + ret = regmap_write(st->regmap, AD4052_REG_TIMER_CONFIG, val); + + iio_device_release_direct(indio_dev); + return ret; +} + +static const struct iio_enum AD4052_500KSPS_sample_rate_enum = { + .items = AD4052_FS(AD4052_500KSPS), + .num_items = AD4052_FS_LEN(AD4052_500KSPS), + .set = ad4052_sample_rate_set, + .get = ad4052_sample_rate_get, +}; + +static const struct iio_enum AD4052_2MSPS_sample_rate_enum = { + .items = AD4052_FS(AD4052_2MSPS), + .num_items = AD4052_FS_LEN(AD4052_2MSPS), + .set = ad4052_sample_rate_set, + .get = ad4052_sample_rate_get, +}; + +#define AD4052_EXT_INFO(grade) \ +static struct iio_chan_spec_ext_info grade##_ext_info[] = { \ + IIO_ENUM("sample_rate", IIO_SHARED_BY_ALL, &grade##_sample_rate_enum), \ + IIO_ENUM_AVAILABLE("sample_rate", IIO_SHARED_BY_ALL, &grade##_sample_rate_enum),\ + {} \ +} + +AD4052_EXT_INFO(AD4052_2MSPS); +AD4052_EXT_INFO(AD4052_500KSPS); + +#define AD4052_CHAN(bits, grade) { \ + .type = IIO_VOLTAGE, \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .indexed = 1, \ + .channel = 0, \ + .event_spec = ad4052_events, \ + .num_event_specs = ARRAY_SIZE(ad4052_events), \ + .has_ext_scan_type = 1, \ + .ext_scan_type = ad4052_scan_type_##bits##_s, \ + .num_ext_scan_type = ARRAY_SIZE(ad4052_scan_type_##bits##_s), \ + .ext_info = grade##_ext_info, \ +} + +#define AD4052_OFFLOAD_CHAN(bits, grade) { \ + .type = IIO_VOLTAGE, \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .indexed = 1, \ + .channel = 0, \ + .event_spec = ad4052_events, \ + .num_event_specs = ARRAY_SIZE(ad4052_events), \ + .has_ext_scan_type = 1, \ + .ext_scan_type = ad4052_scan_type_##bits##_s, \ + .num_ext_scan_type = ARRAY_SIZE(ad4052_scan_type_##bits##_s), \ + .ext_info = grade##_ext_info, \ +} + +const struct ad4052_chip_info ad4050_chip_info = { + .name = "ad4050", + .channels = { AD4052_CHAN(12, AD4052_2MSPS) }, + .offload_channels = { AD4052_OFFLOAD_CHAN(12, AD4052_2MSPS) }, + .prod_id = 0x70, + .max_avg = AD4050_MAX_AVG, + .grade = AD4052_2MSPS, +}; + +const struct ad4052_chip_info ad4052_chip_info = { + .name = "ad4052", + .channels = { AD4052_CHAN(16, AD4052_2MSPS) }, + .offload_channels = { AD4052_OFFLOAD_CHAN(16, AD4052_2MSPS) }, + .prod_id = 0x72, + .max_avg = AD4052_MAX_AVG, + .grade = AD4052_2MSPS, +}; + +const struct ad4052_chip_info ad4056_chip_info = { + .name = "ad4056", + .channels = { AD4052_CHAN(12, AD4052_500KSPS) }, + .offload_channels = { AD4052_OFFLOAD_CHAN(12, AD4052_500KSPS) }, + .prod_id = 0x70, + .max_avg = AD4050_MAX_AVG, + .grade = AD4052_500KSPS, +}; + +const struct ad4052_chip_info ad4058_chip_info = { + .name = "ad4058", + .channels = { AD4052_CHAN(16, AD4052_500KSPS) }, + .offload_channels = { AD4052_OFFLOAD_CHAN(16, AD4052_500KSPS) }, + .prod_id = 0x72, + .max_avg = AD4052_MAX_AVG, + .grade = AD4052_500KSPS, +}; + +static void ad4052_update_xfer_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad4052_state *st = iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + struct spi_transfer *xfer = &st->xfer; + + scan_type = iio_get_current_scan_type(indio_dev, chan); + + xfer->bits_per_word = scan_type->realbits; + xfer->len = BITS_TO_BYTES(scan_type->storagebits); +} + +static int ad4052_update_xfer_offload(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad4052_state *st = iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + struct spi_transfer *xfer = &st->xfer; + + scan_type = iio_get_current_scan_type(indio_dev, chan); + + xfer = &st->offload_xfer; + xfer->bits_per_word = scan_type->realbits; + xfer->len = BITS_TO_BYTES(scan_type->storagebits); + + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); + st->offload_msg.offload = st->offload; + + return spi_optimize_message(st->spi, &st->offload_msg); +} + +static int ad4052_set_oversampling_ratio(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + if (AD4052_CHECK_OVERSAMPLING(st->chip->max_avg, val)) + return -EINVAL; + + /* 0 or 1 disables oversampling */ + if (val == 0 || val == 1) { + st->mode = AD4052_SAMPLE_MODE; + } else { + val = ilog2(val); + st->mode = AD4052_BURST_AVERAGING_MODE; + ret = regmap_write(st->regmap, AD4052_REG_AVG_CONFIG, val - 1); + if (ret) + return ret; + } + + ad4052_update_xfer_raw(indio_dev, chan); + + return 0; +} + +static int ad4052_get_oversampling_ratio(struct ad4052_state *st, + unsigned int *val) +{ + int ret; + + if (st->mode == AD4052_SAMPLE_MODE) { + *val = 0; + return 0; + } + + ret = regmap_read(st->regmap, AD4052_REG_AVG_CONFIG, val); + if (ret) + return ret; + + *val = BIT(*val + 1); + + return 0; +} + +static int ad4052_assert(struct ad4052_state *st) +{ + int ret; + u16 val; + + ret = regmap_bulk_read(st->regmap, AD4052_REG_PROD_ID_1, &st->d16, 2); + if (ret) + return ret; + + val = be16_to_cpu(st->d16); + if (val != st->chip->prod_id) + return -ENODEV; + + ret = regmap_bulk_read(st->regmap, AD4052_REG_VENDOR_H, &st->d16, 2); + if (ret) + return ret; + + val = be16_to_cpu(st->d16); + if (val != AD4052_SPI_VENDOR) + return -ENODEV; + + return 0; +} + +static int ad4052_exit_command(struct ad4052_state *st) +{ + struct spi_device *spi = st->spi; + const u8 val = 0xA8; + + return spi_write(spi, &val, 1); +} + +static int ad4052_set_operation_mode(struct ad4052_state *st, enum ad4052_operation_mode mode) +{ + u8 val = st->data_format | mode; + int ret; + + ret = regmap_write(st->regmap, AD4052_REG_ADC_MODES, val); + if (ret) + return ret; + + val = BIT(0); + return regmap_write(st->regmap, AD4052_REG_MODE_SET, val); +} + +static int __ad4052_set_sampling_freq(struct ad4052_state *st, unsigned int freq) +{ + struct spi_offload_trigger_config config = { + .type = SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic = { + .frequency_hz = freq, + }, + }; + int ret; + + ret = spi_offload_trigger_validate(st->offload_trigger, &config); + if (ret) + return ret; + + st->offload_trigger_hz = config.periodic.frequency_hz; + + return 0; +} + +static int ad4052_soft_reset(struct ad4052_state *st) +{ + int ret; + + memset(st->buf_reset_pattern, 0xFF, sizeof(st->buf_reset_pattern)); + for (int i = 0; i < 3; i++) + st->buf_reset_pattern[6 * (i + 1) - 1] = 0xFE; + + ret = spi_write(st->spi, st->buf_reset_pattern, + sizeof(st->buf_reset_pattern)); + if (ret) + return ret; + + /* Wait AD4052 reset delay */ + fsleep(5000); + + return 0; +} + +static int ad4052_set_non_defaults(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad4052_state *st = iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + + scan_type = iio_get_current_scan_type(indio_dev, chan); + + u8 val = FIELD_PREP(AD4052_GP_MODE_MSK(0), AD4052_GP_INTR) | + FIELD_PREP(AD4052_GP_MODE_MSK(1), AD4052_GP_DRDY); + int ret; + + ret = regmap_update_bits(st->regmap, AD4052_REG_GP_CONFIG, + AD4052_GP_MODE_MSK(1) | AD4052_GP_MODE_MSK(0), + val); + if (ret) + return ret; + + val = FIELD_PREP(AD4052_INTR_EN_MSK(0), (AD4052_INTR_EN_EITHER)) | + FIELD_PREP(AD4052_INTR_EN_MSK(1), (AD4052_INTR_EN_NEITHER)); + + ret = regmap_update_bits(st->regmap, AD4052_REG_INTR_CONFIG, + AD4052_INTR_EN_MSK(0) | AD4052_INTR_EN_MSK(1), + val); + if (ret) + return ret; + + val = 0; + if (scan_type->sign == 's') + val |= AD4052_DATA_FORMAT; + + st->data_format = val; + + if (st->chip->grade == AD4052_500KSPS) { + ret = regmap_write(st->regmap, AD4052_REG_TIMER_CONFIG, + FIELD_PREP(AD4052_FS_MASK, AD4052_300KSPS)); + if (ret) + return ret; + } + + return regmap_write(st->regmap, AD4052_REG_ADC_MODES, val); +} + +static irqreturn_t ad4052_irq_handler_thresh(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_EITHER), + iio_get_time_ns(indio_dev)); + + return IRQ_HANDLED; +} + +static irqreturn_t ad4052_irq_handler_drdy(int irq, void *private) +{ + struct ad4052_state *st = private; + + complete(&st->completion); + + return IRQ_HANDLED; +} + +static int ad4052_request_irq(struct iio_dev *indio_dev) +{ + struct ad4052_state *st = iio_priv(indio_dev); + struct device *dev = &st->spi->dev; + int ret = 0; + + ret = fwnode_irq_get(dev_fwnode(&st->spi->dev), 0); + if (ret <= 0) + return ret ? ret : -EINVAL; + + ret = devm_request_threaded_irq(dev, + ret, NULL, ad4052_irq_handler_thresh, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return ret; + + ret = fwnode_irq_get(dev_fwnode(&st->spi->dev), 1); + if (ret <= 0) + return ret ? ret : -EINVAL; + + st->gp1_irq = ret; + ret = devm_request_threaded_irq(dev, + ret, NULL, ad4052_irq_handler_drdy, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + indio_dev->name, st); + return ret; +} + +static const int ad4052_oversampling_avail[] = { + 0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096 +}; + +static int ad4052_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, const int **vals, + int *type, int *len, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals = ad4052_oversampling_avail; + *len = ARRAY_SIZE(ad4052_oversampling_avail); + *type = IIO_VAL_INT; + + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static ssize_t ad4052_set_sampling_freq(struct ad4052_state *st, unsigned int val) +{ + int ret; + + if (AD4052_CHECK_RATE(st->chip->grade, val)) + return -EINVAL; + + ret = __ad4052_set_sampling_freq(st, val); + + return ret; +} + +static int __ad4052_read_chan_raw(struct ad4052_state *st, int *val) +{ + struct spi_device *spi = st->spi; + int ret; + struct spi_transfer t_cnv = { + .len = 0 + }; + + reinit_completion(&st->completion); + + if (st->cnv_gp) { + gpiod_set_value_cansleep(st->cnv_gp, 1); + gpiod_set_value_cansleep(st->cnv_gp, 0); + } else { + ret = spi_sync_transfer(spi, &t_cnv, 1); + if (ret) + return ret; + } + /* + * Single sample read should be used only for oversampling and + * sampling frequency pairs that take less than 1 sec. + */ + ret = wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + if (!ret) + return -ETIMEDOUT; + + ret = spi_sync_transfer(spi, &st->xfer, 1); + if (ret) + return ret; + + if (st->xfer.len == 2) { + *val = st->d16; + if (st->data_format & AD4052_DATA_FORMAT) + *val = sign_extend32(*val, 15); + } else { + *val = st->d32; + if (st->data_format & AD4052_DATA_FORMAT) + *val = sign_extend32(*val, 23); + } + + return ret; +} + +static int ad4052_read_chan_raw(struct iio_dev *indio_dev, int *val) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + ret = pm_runtime_resume_and_get(&st->spi->dev); + if (ret) + return ret; + + ret = ad4052_set_operation_mode(st, st->mode); + if (ret) + goto out_error; + + ret = __ad4052_read_chan_raw(st, val); + if (ret) + goto out_error; + + ret = ad4052_exit_command(st); + +out_error: + pm_runtime_mark_last_busy(&st->spi->dev); + pm_runtime_put_autosuspend(&st->spi->dev); + return ret; +} + +static int ad4052_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = ad4052_read_chan_raw(indio_dev, val); + if (ret) + goto out_release; + ret = IIO_VAL_INT; + break; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret = ad4052_get_oversampling_ratio(st, val); + if (ret) + goto out_release; + ret = IIO_VAL_INT; + break; + case IIO_CHAN_INFO_SAMP_FREQ: + *val = st->offload_trigger_hz; + ret = IIO_VAL_INT; + break; + default: + ret = -EINVAL; + } + +out_release: + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4052_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long info) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + switch (info) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret = ad4052_set_oversampling_ratio(indio_dev, chan, val); + break; + case IIO_CHAN_INFO_SAMP_FREQ: + ret = ad4052_set_sampling_freq(st, val); + break; + default: + ret = -EINVAL; + } + + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4052_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret, state; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + ret = regmap_read(st->regmap, AD4052_REG_GP_CONFIG, &state); + + iio_device_release_direct(indio_dev); + return ret ? ret : state & AD4052_GP_MODE_MSK(0); +} + +static int ad4052_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret = -EBUSY; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + if (st->wait_event == state) + goto out_release; + + if (state) { + ret = pm_runtime_resume_and_get(&st->spi->dev); + if (ret) + goto out_release; + + ret = ad4052_set_operation_mode(st, AD4052_MONITOR_MODE); + if (ret) + goto out_err_suspend; + } else { + pm_runtime_mark_last_busy(&st->spi->dev); + pm_runtime_put_autosuspend(&st->spi->dev); + + ret = ad4052_exit_command(st); + } + st->wait_event = state; + iio_device_release_direct(indio_dev); + return ret; + +out_err_suspend: + pm_runtime_mark_last_busy(&st->spi->dev); + pm_runtime_put_autosuspend(&st->spi->dev); + +out_release: + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4052_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int *val, + int *val2) +{ + struct ad4052_state *st = iio_priv(indio_dev); + u8 reg, size = 1; + int ret; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + switch (info) { + case IIO_EV_INFO_VALUE: + if (dir == IIO_EV_DIR_RISING) + reg = AD4052_REG_MAX_LIMIT; + else + reg = AD4052_REG_MIN_LIMIT; + size++; + break; + case IIO_EV_INFO_HYSTERESIS: + if (dir == IIO_EV_DIR_RISING) + reg = AD4052_REG_MAX_HYST; + else + reg = AD4052_REG_MIN_HYST; + break; + default: + iio_device_release_direct(indio_dev); + return -EINVAL; + } + + ret = regmap_bulk_read(st->regmap, reg, &st->d32, size); + if (ret) { + iio_device_release_direct(indio_dev); + return ret; + } + + if (reg == AD4052_REG_MAX_LIMIT || reg == AD4052_REG_MIN_LIMIT) { + *val = be16_to_cpu(st->d16); + if (st->data_format & AD4052_DATA_FORMAT) + *val = sign_extend32(*val, 11); + } else { + *val = st->d32; + } + + iio_device_release_direct(indio_dev); + return IIO_VAL_INT; +} + +static int ad4052_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int val, + int val2) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret = -EINVAL; + u8 reg, size = 1; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + st->d16 = cpu_to_be16(val); + + switch (type) { + case IIO_EV_TYPE_THRESH: + switch (info) { + case IIO_EV_INFO_VALUE: + if (st->data_format & AD4052_DATA_FORMAT) { + if (val > 2047 || val < -2048) + goto out_release; + } else if (val > 4095 || val < 0) { + goto out_release; + } + if (dir == IIO_EV_DIR_RISING) + reg = AD4052_REG_MAX_LIMIT; + else + reg = AD4052_REG_MIN_LIMIT; + size++; + break; + case IIO_EV_INFO_HYSTERESIS: + if (val & BIT(7)) + goto out_release; + if (dir == IIO_EV_DIR_RISING) + reg = AD4052_REG_MAX_HYST; + else + reg = AD4052_REG_MIN_HYST; + st->d16 >>= 8; + break; + default: + goto out_release; + } + break; + default: + goto out_release; + } + + ret = regmap_bulk_write(st->regmap, reg, &st->d16, size); + +out_release: + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4052_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad4052_state *st = iio_priv(indio_dev); + struct spi_offload_trigger_config config = { + .type = SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic = { + .frequency_hz = st->offload_trigger_hz, + }, + }; + int ret; + + if (st->wait_event) + return -EBUSY; + + ret = pm_runtime_resume_and_get(&st->spi->dev); + if (ret) + return ret; + + ret = ad4052_set_operation_mode(st, st->mode); + if (ret) + goto out_error; + + ret = ad4052_update_xfer_offload(indio_dev, indio_dev->channels); + if (ret) + goto out_error; + + disable_irq(st->gp1_irq); + + ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, + &config); + if (ret) + goto out_offload_error; + + return 0; + +out_offload_error: + enable_irq(st->gp1_irq); +out_error: + pm_runtime_mark_last_busy(&st->spi->dev); + pm_runtime_put_autosuspend(&st->spi->dev); + + return ret; +} + +static int ad4052_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + spi_unoptimize_message(&st->offload_msg); + enable_irq(st->gp1_irq); + + ret = ad4052_exit_command(st); + + pm_runtime_mark_last_busy(&st->spi->dev); + pm_runtime_put_autosuspend(&st->spi->dev); + + return ret; +} + +static const struct iio_buffer_setup_ops ad4052_buffer_setup_ops = { + .preenable = &ad4052_buffer_preenable, + .postdisable = &ad4052_buffer_postdisable, +}; + +static int ad4052_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4052_state *st = iio_priv(indio_dev); + int ret; + + if (!ad4052_iio_device_claim_direct(indio_dev, st)) + return -EBUSY; + + if (readval) + ret = regmap_read(st->regmap, reg, readval); + else + ret = regmap_write(st->regmap, reg, writeval); + + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4052_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad4052_state *st = iio_priv(indio_dev); + + /* + * REVISIT: the supported offload has a fixed length of 32-bits + * to fit the 24-bits oversampled case, requiring the additional + * offload scan types. + */ + if (iio_buffer_enabled(indio_dev)) + return st->mode == AD4052_BURST_AVERAGING_MODE ? + AD4052_SCAN_TYPE_OFFLOAD_BURST_AVG : + AD4052_SCAN_TYPE_OFFLOAD_SAMPLE; + + return st->mode == AD4052_BURST_AVERAGING_MODE ? + AD4052_SCAN_TYPE_BURST_AVG : + AD4052_SCAN_TYPE_SAMPLE; +} + +static const struct iio_info ad4052_info = { + .read_raw = ad4052_read_raw, + .write_raw = ad4052_write_raw, + .read_avail = ad4052_read_avail, + .read_event_config = &ad4052_read_event_config, + .write_event_config = &ad4052_write_event_config, + .read_event_value = &ad4052_read_event_value, + .write_event_value = &ad4052_write_event_value, + .get_current_scan_type = &ad4052_get_current_scan_type, + .debugfs_reg_access = &ad4052_debugfs_reg_access, +}; + +static const struct regmap_config ad4052_regmap_config = { + .name = "ad4052", + .reg_bits = 8, + .val_bits = 8, + .max_register = AD4052_MAX_REG, + .read_flag_mask = BIT(7), + .can_sleep = true, +}; + +static const struct spi_offload_config ad4052_offload_config = { + .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static int ad4052_request_offload(struct iio_dev *indio_dev) +{ + struct ad4052_state *st = iio_priv(indio_dev); + struct device *dev = &st->spi->dev; + struct dma_chan *rx_dma; + int ret; + + indio_dev->setup_ops = &ad4052_buffer_setup_ops; + + st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; + st->offload_trigger = devm_spi_offload_trigger_get(dev, + st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + + if (IS_ERR(st->offload_trigger)) + return PTR_ERR(st->offload_trigger); + + ret = __ad4052_set_sampling_freq(st, AD4052_MAX_RATE(st->chip->grade)); + if (ret) + return ret; + + rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, + st->offload); + if (IS_ERR(rx_dma)) + return PTR_ERR(rx_dma); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + +static int ad4052_probe(struct spi_device *spi) +{ + const struct ad4052_chip_info *chip; + struct device *dev = &spi->dev; + struct iio_dev *indio_dev; + struct ad4052_state *st; + int ret; + u8 buf; + + chip = spi_get_device_match_data(spi); + if (!chip) + return dev_err_probe(dev, -ENODEV, + "Could not find chip info data\n"); + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->spi = spi; + spi_set_drvdata(spi, st); + init_completion(&st->completion); + + st->regmap = devm_regmap_init_spi(spi, &ad4052_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(&spi->dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + st->mode = AD4052_SAMPLE_MODE; + st->wait_event = false; + st->chip = chip; + + st->cnv_gp = devm_gpiod_get_optional(dev, "cnv", + GPIOD_OUT_LOW); + if (IS_ERR(st->cnv_gp)) + return dev_err_probe(dev, PTR_ERR(st->cnv_gp), + "Failed to get cnv gpio\n"); + + indio_dev->modes = INDIO_BUFFER_HARDWARE | INDIO_DIRECT_MODE; + indio_dev->num_channels = 1; + indio_dev->info = &ad4052_info; + indio_dev->name = chip->name; + + st->offload = devm_spi_offload_get(dev, spi, &ad4052_offload_config); + ret = PTR_ERR_OR_ZERO(st->offload); + if (ret && ret != -ENODEV) + return dev_err_probe(dev, ret, "Failed to get offload\n"); + + if (ret == -ENODEV) { + st->offload_trigger = NULL; + indio_dev->channels = chip->channels; + } else { + indio_dev->channels = chip->offload_channels; + ret = ad4052_request_offload(indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure offload\n"); + } + + st->xfer.rx_buf = &st->d32; + + ret = ad4052_soft_reset(st); + if (ret) + return dev_err_probe(dev, ret, + "AD4052 failed to soft reset\n"); + + ret = ad4052_assert(st); + if (ret) + return dev_err_probe(dev, ret, + "AD4052 fields assertions failed\n"); + + ret = ad4052_set_non_defaults(indio_dev, indio_dev->channels); + if (ret) + return ret; + + buf = AD4052_DEVICE_RESET; + ret = regmap_write(st->regmap, AD4052_REG_DEVICE_STATUS, buf); + if (ret) + return ret; + + ret = ad4052_request_irq(indio_dev); + if (ret) + return ret; + + ad4052_update_xfer_raw(indio_dev, indio_dev->channels); + + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + pm_runtime_set_active(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable pm_runtime\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static int ad4052_runtime_suspend(struct device *dev) +{ + u8 val = FIELD_PREP(AD4052_POWER_MODE_MSK, AD4052_LOW_POWER_MODE); + struct ad4052_state *st = dev_get_drvdata(dev); + + return regmap_write(st->regmap, AD4052_REG_DEVICE_CONFIG, val); +} + +static int ad4052_runtime_resume(struct device *dev) +{ + struct ad4052_state *st = dev_get_drvdata(dev); + u8 val = FIELD_PREP(AD4052_POWER_MODE_MSK, 0); + int ret; + + ret = regmap_write(st->regmap, AD4052_REG_DEVICE_CONFIG, val); + if (ret) + return ret; + + fsleep(2000); + return 0; +} + +static const struct dev_pm_ops ad4052_pm_ops = { + RUNTIME_PM_OPS(ad4052_runtime_suspend, ad4052_runtime_resume, NULL) +}; + +static const struct spi_device_id ad4052_id_table[] = { + {"ad4050", (kernel_ulong_t)&ad4050_chip_info }, + {"ad4052", (kernel_ulong_t)&ad4052_chip_info }, + {"ad4056", (kernel_ulong_t)&ad4056_chip_info }, + {"ad4058", (kernel_ulong_t)&ad4058_chip_info }, + {} +}; +MODULE_DEVICE_TABLE(spi, ad4052_id_table); + +static const struct of_device_id ad4052_of_match[] = { + { .compatible = "adi,ad4050", .data = &ad4050_chip_info }, + { .compatible = "adi,ad4052", .data = &ad4052_chip_info }, + { .compatible = "adi,ad4056", .data = &ad4056_chip_info }, + { .compatible = "adi,ad4058", .data = &ad4058_chip_info }, + {} +}; +MODULE_DEVICE_TABLE(of, ad4052_of_match); + +static struct spi_driver ad4052_driver = { + .driver = { + .name = "ad4052", + .of_match_table = ad4052_of_match, + .pm = pm_ptr(&ad4052_pm_ops), + }, + .probe = ad4052_probe, + .id_table = ad4052_id_table, +}; +module_spi_driver(ad4052_driver); + +MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); +MODULE_DESCRIPTION("Analog Devices AD4052"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
The AD4052/AD4058/AD4050/AD4056 are versatile, 16-bit/12-bit, successive approximation register (SAR) analog-to-digital converter (ADC) that enables low-power, high-density data acquisition solutions without sacrificing precision. This ADC offers a unique balance of performance and power efficiency, plus innovative features for seamlessly switching between high-resolution and low-power modes tailored to the immediate needs of the system. The AD4052/AD4058/AD4050/AD4056 are ideal for battery-powered, compact data acquisition and edge sensing applications. Signed-off-by: Jorge Marques <jorge.marques@analog.com> --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 14 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4052.c | 1289 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1305 insertions(+)