| Message ID | 20250308-phy-sam-hdptx-bpc-v5-3-35087287f9d1@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | phy: rockchip: samsung-hdptx: Support high color depth management | expand |
On Sat, 8 Mar 2025 at 14:21, Cristian Ciocaltea <cristian.ciocaltea@collabora.com> wrote: > > The switch from 1/10 to 1/40 clock ratio must happen when exceeding the > 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, > and not before. Am I correct that the only functional change is a switch from greater-or-equal to simple greater? > > While at it, introduce a define for this rate limit constant. > > Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > index f88369864c50e4563834ccbb26f1f9f440e99271..cf2c3a46604cb9d8c26fe5ec8346904e0b62848f 100644 > --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > @@ -320,6 +320,7 @@ > #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) > #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) > > +#define HDMI14_MAX_RATE 340000000 > #define HDMI20_MAX_RATE 600000000 > > enum dp_link_rate { > @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, > > regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); > > - if (rate >= 3400000) { > + if (rate > HDMI14_MAX_RATE / 100) { > /* For 1/40 bitrate clk */ > rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); > } else { > > -- > 2.48.1 >
On 3/9/25 11:17 AM, Dmitry Baryshkov wrote: > On Sat, 8 Mar 2025 at 14:21, Cristian Ciocaltea > <cristian.ciocaltea@collabora.com> wrote: >> >> The switch from 1/10 to 1/40 clock ratio must happen when exceeding the >> 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, >> and not before. > > Am I correct that the only functional change is a switch from > greater-or-equal to simple greater? Yes.
On Sun, 9 Mar 2025 at 12:11, Cristian Ciocaltea <cristian.ciocaltea@collabora.com> wrote: > > On 3/9/25 11:17 AM, Dmitry Baryshkov wrote: > > On Sat, 8 Mar 2025 at 14:21, Cristian Ciocaltea > > <cristian.ciocaltea@collabora.com> wrote: > >> > >> The switch from 1/10 to 1/40 clock ratio must happen when exceeding the > >> 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, > >> and not before. > > > > Am I correct that the only functional change is a switch from > > greater-or-equal to simple greater? > > Yes. If you were to repost the series for any reason, could you please spell that explicitly in the commit message. If not, it's fine. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 3/9/25 12:12 PM, Dmitry Baryshkov wrote: > On Sun, 9 Mar 2025 at 12:11, Cristian Ciocaltea > <cristian.ciocaltea@collabora.com> wrote: >> >> On 3/9/25 11:17 AM, Dmitry Baryshkov wrote: >>> On Sat, 8 Mar 2025 at 14:21, Cristian Ciocaltea >>> <cristian.ciocaltea@collabora.com> wrote: >>>> >>>> The switch from 1/10 to 1/40 clock ratio must happen when exceeding the >>>> 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, >>>> and not before. >>> >>> Am I correct that the only functional change is a switch from >>> greater-or-equal to simple greater? >> >> Yes. > > If you were to repost the series for any reason, could you please > spell that explicitly in the commit message. If not, it's fine. Sure, I'll handle it in v6. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Thanks, Cristian
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index f88369864c50e4563834ccbb26f1f9f440e99271..cf2c3a46604cb9d8c26fe5ec8346904e0b62848f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -320,6 +320,7 @@ #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) +#define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 enum dp_link_rate { @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); - if (rate >= 3400000) { + if (rate > HDMI14_MAX_RATE / 100) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else {
The switch from 1/10 to 1/40 clock ratio must happen when exceeding the 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, and not before. While at it, introduce a define for this rate limit constant. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)