| Message ID | 20250310210340.3234884-4-alejandro.lucero-palau@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | add type2 device basic support | expand |
On 3/10/25 4:03 PM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Inside cxl/core/pci.c there are helpers for CXL PCIe initialization > meanwhile cxl/pci.c implements the functionality for a Type3 device > initialization. > > Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be > exported and shared with CXL Type2 device initialization. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- [snip] > diff --git a/include/cxl/pci.h b/include/cxl/pci.h > index ad63560caa2c..e6178aa341b2 100644 > --- a/include/cxl/pci.h > +++ b/include/cxl/pci.h > @@ -1,8 +1,21 @@ > /* SPDX-License-Identifier: GPL-2.0-only */ > /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ > > -#ifndef __CXL_ACCEL_PCI_H > -#define __CXL_ACCEL_PCI_H > +#ifndef __LINUX_CXL_PCI_H > +#define __LINUX_CXL_PCI_H Should probably just change this to __LINUX_CXL_PCI_H in the last patch when creating the file. With that: Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> > + > +#include <linux/pci.h> > + > +/* > + * Assume that the caller has already validated that @pdev has CXL > + * capabilities, any RCIEp with CXL capabilities is treated as a > + * Restricted CXL Device (RCD) and finds upstream port and endpoint > + * registers in a Root Complex Register Block (RCRB). > + */ > +static inline bool is_cxl_restricted(struct pci_dev *pdev) > +{ > + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; > +} > > /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ > #define CXL_DVSEC_PCIE_DEVICE 0 > diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild > index ef10a896a384..f20df22bddd2 100644 > --- a/tools/testing/cxl/Kbuild > +++ b/tools/testing/cxl/Kbuild > @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready > ldflags-y += --wrap=cxl_hdm_decode_init > ldflags-y += --wrap=cxl_dvsec_rr_decode > ldflags-y += --wrap=devm_cxl_add_rch_dport > -ldflags-y += --wrap=cxl_rcd_component_reg_phys > ldflags-y += --wrap=cxl_endpoint_parse_cdat > ldflags-y += --wrap=cxl_dport_init_ras_reporting > > diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c > index af2594e4f35d..3c6a071fbbe3 100644 > --- a/tools/testing/cxl/test/mock.c > +++ b/tools/testing/cxl/test/mock.c > @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, > } > EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); > > -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, > - struct cxl_dport *dport) > -{ > - int index; > - resource_size_t component_reg_phys; > - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > - > - if (ops && ops->is_mock_port(dev)) > - component_reg_phys = CXL_RESOURCE_NONE; > - else > - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); > - put_cxl_mock_ops(index); > - > - return component_reg_phys; > -} > -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); > - > void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) > { > int index;
On 3/11/25 20:05, Ben Cheatham wrote: > On 3/10/25 4:03 PM, alejandro.lucero-palau@amd.com wrote: >> From: Alejandro Lucero <alucerop@amd.com> >> >> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization >> meanwhile cxl/pci.c implements the functionality for a Type3 device >> initialization. >> >> Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be >> exported and shared with CXL Type2 device initialization. >> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> Reviewed-by: Dave Jiang <dave.jiang@intel.com> >> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> >> Reviewed-by: Fan Ni <fan.ni@samsung.com> >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> >> --- > [snip] > >> diff --git a/include/cxl/pci.h b/include/cxl/pci.h >> index ad63560caa2c..e6178aa341b2 100644 >> --- a/include/cxl/pci.h >> +++ b/include/cxl/pci.h >> @@ -1,8 +1,21 @@ >> /* SPDX-License-Identifier: GPL-2.0-only */ >> /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ >> >> -#ifndef __CXL_ACCEL_PCI_H >> -#define __CXL_ACCEL_PCI_H >> +#ifndef __LINUX_CXL_PCI_H >> +#define __LINUX_CXL_PCI_H > Should probably just change this to __LINUX_CXL_PCI_H in the last patch > when creating the file. Yes, this is biting me again. I'll do so. Thanks > With that: > Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> > >> + >> +#include <linux/pci.h> >> + >> +/* >> + * Assume that the caller has already validated that @pdev has CXL >> + * capabilities, any RCIEp with CXL capabilities is treated as a >> + * Restricted CXL Device (RCD) and finds upstream port and endpoint >> + * registers in a Root Complex Register Block (RCRB). >> + */ >> +static inline bool is_cxl_restricted(struct pci_dev *pdev) >> +{ >> + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; >> +} >> >> /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ >> #define CXL_DVSEC_PCIE_DEVICE 0 >> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild >> index ef10a896a384..f20df22bddd2 100644 >> --- a/tools/testing/cxl/Kbuild >> +++ b/tools/testing/cxl/Kbuild >> @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready >> ldflags-y += --wrap=cxl_hdm_decode_init >> ldflags-y += --wrap=cxl_dvsec_rr_decode >> ldflags-y += --wrap=devm_cxl_add_rch_dport >> -ldflags-y += --wrap=cxl_rcd_component_reg_phys >> ldflags-y += --wrap=cxl_endpoint_parse_cdat >> ldflags-y += --wrap=cxl_dport_init_ras_reporting >> >> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c >> index af2594e4f35d..3c6a071fbbe3 100644 >> --- a/tools/testing/cxl/test/mock.c >> +++ b/tools/testing/cxl/test/mock.c >> @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, >> } >> EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); >> >> -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, >> - struct cxl_dport *dport) >> -{ >> - int index; >> - resource_size_t component_reg_phys; >> - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); >> - >> - if (ops && ops->is_mock_port(dev)) >> - component_reg_phys = CXL_RESOURCE_NONE; >> - else >> - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); >> - put_cxl_mock_ops(index); >> - >> - return component_reg_phys; >> -} >> -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); >> - >> void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) >> { >> int index;
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 3d3b00835446..167553d8f10b 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -109,6 +109,8 @@ enum cxl_poison_trace_type { CXL_POISON_TRACE_CLEAR, }; +resource_size_t cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); long cxl_pci_get_latency(struct pci_dev *pdev); int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 2e9af4898914..0b8dc34b8300 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1033,6 +1033,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map, + struct cxl_dport *dport) +{ + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + struct cxl_port *port __free(put_cxl_port) = + cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) { + struct cxl_dport *dport; + struct cxl_port *port __free(put_cxl_port) = + cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + rc = cxl_rcrb_get_comp_regs(pdev, map, dport); + if (rc) + return rc; + + rc = cxl_dport_map_rcd_linkcap(pdev, dport); + if (rc) + return rc; + + } else if (rc) { + return rc; + } + + return cxl_setup_regs(map); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 58a942a4946c..be0ae9aca84a 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -646,4 +646,3 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev, return CXL_RESOURCE_NONE; return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); } -EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index fd7e2f3811a2..5d608975ca38 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -221,8 +221,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); int cxl_setup_regs(struct cxl_register_map *map); struct cxl_dport; -resource_size_t cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport); int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 570e53e26f11..0611d96d76da 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -114,4 +114,6 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 769db8edf608..e8c0efb3a12f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -467,76 +467,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map, - struct cxl_dport *dport) -{ - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) { - struct cxl_dport *dport; - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - rc = cxl_rcrb_get_comp_regs(pdev, map, dport); - if (rc) - return rc; - - rc = cxl_dport_map_rcd_linkcap(pdev, dport); - if (rc) - return rc; - - } else if (rc) { - return rc; - } - - return cxl_setup_regs(map); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); diff --git a/include/cxl/pci.h b/include/cxl/pci.h index ad63560caa2c..e6178aa341b2 100644 --- a/include/cxl/pci.h +++ b/include/cxl/pci.h @@ -1,8 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ -#ifndef __CXL_ACCEL_PCI_H -#define __CXL_ACCEL_PCI_H +#ifndef __LINUX_CXL_PCI_H +#define __LINUX_CXL_PCI_H + +#include <linux/pci.h> + +/* + * Assume that the caller has already validated that @pdev has CXL + * capabilities, any RCIEp with CXL capabilities is treated as a + * Restricted CXL Device (RCD) and finds upstream port and endpoint + * registers in a Root Complex Register Block (RCRB). + */ +static inline bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index ef10a896a384..f20df22bddd2 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready ldflags-y += --wrap=cxl_hdm_decode_init ldflags-y += --wrap=cxl_dvsec_rr_decode ldflags-y += --wrap=devm_cxl_add_rch_dport -ldflags-y += --wrap=cxl_rcd_component_reg_phys ldflags-y += --wrap=cxl_endpoint_parse_cdat ldflags-y += --wrap=cxl_dport_init_ras_reporting diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index af2594e4f35d..3c6a071fbbe3 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport) -{ - int index; - resource_size_t component_reg_phys; - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - - if (ops && ops->is_mock_port(dev)) - component_reg_phys = CXL_RESOURCE_NONE; - else - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); - put_cxl_mock_ops(index); - - return component_reg_phys; -} -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); - void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) { int index;