| Message ID | 20250306-videocc-pll-multi-pd-voting-v2-1-0cd00612bc0e@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On Thu, Mar 06, 2025 at 02:25:33PM +0530, Jagadeesh Kona wrote: > To configure the video PLLs and enable the video GDSCs on SM8450, > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along > with MMCX. Therefore, update the videocc bindings to include > the MXC power domain on these platforms. > > Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Acked-by: Rob Herring (Arm) <robh@kernel.org> > --- > Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -32,9 +32,11 @@ properties: > - description: Video AHB clock from GCC > > power-domains: > - maxItems: 1 > description: > - MMCX power domain. > + Power domains required for the clock controller to operate > + items: > + - description: MMCX power domain > + - description: MXC power domain > > required-opps: > maxItems: 1 > @@ -72,7 +74,8 @@ examples: > reg = <0x0aaf0000 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > required-opps = <&rpmhpd_opp_low_svs>; As pointed out by Vladimir, you probably also need a second entry in required-opps. > #clock-cells = <1>; > #reset-cells = <1>; > > -- > 2.34.1 >
On 3/6/2025 3:40 PM, Dmitry Baryshkov wrote: > On Thu, Mar 06, 2025 at 02:25:33PM +0530, Jagadeesh Kona wrote: >> To configure the video PLLs and enable the video GDSCs on SM8450, >> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along >> with MMCX. Therefore, update the videocc bindings to include >> the MXC power domain on these platforms. >> >> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >> Acked-by: Rob Herring (Arm) <robh@kernel.org> >> --- >> Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> @@ -32,9 +32,11 @@ properties: >> - description: Video AHB clock from GCC >> >> power-domains: >> - maxItems: 1 >> description: >> - MMCX power domain. >> + Power domains required for the clock controller to operate >> + items: >> + - description: MMCX power domain >> + - description: MXC power domain >> >> required-opps: >> maxItems: 1 >> @@ -72,7 +74,8 @@ examples: >> reg = <0x0aaf0000 0x10000>; >> clocks = <&rpmhcc RPMH_CXO_CLK>, >> <&gcc GCC_VIDEO_AHB_CLK>; >> - power-domains = <&rpmhpd RPMHPD_MMCX>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>, >> + <&rpmhpd RPMHPD_MXC>; >> required-opps = <&rpmhpd_opp_low_svs>; > > As pointed out by Vladimir, you probably also need a second entry in > required-opps. > Sure, will check and add second entry in the required-opps. Thanks, Jagadeesh >> #clock-cells = <1>; >> #reset-cells = <1>; >> >> -- >> 2.34.1 >> >
On 06/03/2025 08:55, Jagadeesh Kona wrote: > To configure the video PLLs and enable the video GDSCs on SM8450, > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along > with MMCX. Therefore, update the videocc bindings to include > the MXC power domain on these platforms. > > Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Acked-by: Rob Herring (Arm) <robh@kernel.org> > --- > Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -32,9 +32,11 @@ properties: > - description: Video AHB clock from GCC > > power-domains: > - maxItems: 1 > description: > - MMCX power domain. > + Power domains required for the clock controller to operate > + items: > + - description: MMCX power domain > + - description: MXC power domain > > required-opps: > maxItems: 1 > @@ -72,7 +74,8 @@ examples: > reg = <0x0aaf0000 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&gcc GCC_VIDEO_AHB_CLK>; > - power-domains = <&rpmhpd RPMHPD_MMCX>; > + power-domains = <&rpmhpd RPMHPD_MMCX>, > + <&rpmhpd RPMHPD_MXC>; > required-opps = <&rpmhpd_opp_low_svs>; > #clock-cells = <1>; > #reset-cells = <1>; > > -- > 2.34.1 > > The ordering of these patches is a bit weird with this binding first and then the rest of the bindings later. Also switched my linux-arm-msm email recently so only got the first patch with my RB in my Linaro inbox. Suggest as standard practice when you get review feedback to CC previous reviewers on all patches in subsequent series, especially if you are picking up an RB on one of those patches. TL;DR please cc me on V3. --- bod
On 3/11/25 10:49 AM, Bryan O'Donoghue wrote: > On 06/03/2025 08:55, Jagadeesh Kona wrote: >> To configure the video PLLs and enable the video GDSCs on SM8450, >> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along >> with MMCX. Therefore, update the videocc bindings to include >> the MXC power domain on these platforms. >> >> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >> Acked-by: Rob Herring (Arm) <robh@kernel.org> >> --- >> Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> @@ -32,9 +32,11 @@ properties: >> - description: Video AHB clock from GCC >> >> power-domains: >> - maxItems: 1 >> description: >> - MMCX power domain. >> + Power domains required for the clock controller to operate >> + items: >> + - description: MMCX power domain >> + - description: MXC power domain >> >> required-opps: >> maxItems: 1 >> @@ -72,7 +74,8 @@ examples: >> reg = <0x0aaf0000 0x10000>; >> clocks = <&rpmhcc RPMH_CXO_CLK>, >> <&gcc GCC_VIDEO_AHB_CLK>; >> - power-domains = <&rpmhpd RPMHPD_MMCX>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>, >> + <&rpmhpd RPMHPD_MXC>; >> required-opps = <&rpmhpd_opp_low_svs>; >> #clock-cells = <1>; >> #reset-cells = <1>; >> >> -- >> 2.34.1 >> >> > > The ordering of these patches is a bit weird with this binding first and then the rest of the bindings later. > > Also switched my linux-arm-msm email recently so only got the first patch with my RB in my Linaro inbox. > > Suggest as standard practice when you get review feedback to CC previous reviewers on all patches in subsequent series, especially if you are picking up an RB on one of those patches. > > TL;DR please cc me on V3. If you pick up review tags, running b4 prep -c again will CC the folks Konrad
On 3/11/2025 3:51 PM, Konrad Dybcio wrote: > On 3/11/25 10:49 AM, Bryan O'Donoghue wrote: >> On 06/03/2025 08:55, Jagadeesh Kona wrote: >>> To configure the video PLLs and enable the video GDSCs on SM8450, >>> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along >>> with MMCX. Therefore, update the videocc bindings to include >>> the MXC power domain on these platforms. >>> >>> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >>> Acked-by: Rob Herring (Arm) <robh@kernel.org> >>> --- >>> Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- >>> 1 file changed, 6 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>> index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 >>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >>> @@ -32,9 +32,11 @@ properties: >>> - description: Video AHB clock from GCC >>> >>> power-domains: >>> - maxItems: 1 >>> description: >>> - MMCX power domain. >>> + Power domains required for the clock controller to operate >>> + items: >>> + - description: MMCX power domain >>> + - description: MXC power domain >>> >>> required-opps: >>> maxItems: 1 >>> @@ -72,7 +74,8 @@ examples: >>> reg = <0x0aaf0000 0x10000>; >>> clocks = <&rpmhcc RPMH_CXO_CLK>, >>> <&gcc GCC_VIDEO_AHB_CLK>; >>> - power-domains = <&rpmhpd RPMHPD_MMCX>; >>> + power-domains = <&rpmhpd RPMHPD_MMCX>, >>> + <&rpmhpd RPMHPD_MXC>; >>> required-opps = <&rpmhpd_opp_low_svs>; >>> #clock-cells = <1>; >>> #reset-cells = <1>; >>> >>> -- >>> 2.34.1 >>> >>> >> >> The ordering of these patches is a bit weird with this binding first and then the rest of the bindings later. >> >> Also switched my linux-arm-msm email recently so only got the first patch with my RB in my Linaro inbox. >> >> Suggest as standard practice when you get review feedback to CC previous reviewers on all patches in subsequent series, especially if you are picking up an RB on one of those patches. >> >> TL;DR please cc me on V3. > > If you pick up review tags, running b4 prep -c again will CC the folks > Yes, I ran b4 prep --auto-to-cc, but looks like b4 sent the email in CC only if there is an explicit review tag. For patches that didn't have an explicit review tag, it didn't include in the CC. I will ensure to add Bryan in CC for all patches in v3. Thanks, Jagadeesh > Konrad
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 62714fa54db82491a7a108f7f18a253d737f8d61..737efc4b46564c1e475b02873d2dc124329fb775 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,9 +32,11 @@ properties: - description: Video AHB clock from GCC power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain required-opps: maxItems: 1 @@ -72,7 +74,8 @@ examples: reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>;
To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller") Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)