| Message ID | 20250312111049.197855-1-jarkko.nikula@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates | expand |
On Wed, Mar 12, 2025 at 01:10:46PM +0200, Jarkko Nikula wrote: > Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are > reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the > current driver code and not needed in DMA transfers. > > PIO transfers with v0.5 would require changes to both > core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though. > > For these reasons don't enable signal updates from INTR_STATUS bits 9:0. > > This change gets rid of "unexpected INTR_STATUS" on old v0.5 IP version > and is a no-op for later versions starting from v0.8. submitting-patches.rst don't perfer words: "this change" or "this patch". Get rid of "unexpected INTR_STATUS" on old v0.5 IP version ... And below nit Reviewed-by: Frank Li <Frank.Li@nxp.com> > > Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> > --- > v2: Simplified the last sentence according to Frank Li's suggestion. > --- > drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c > index a71226d7ca59..e139d7e4d252 100644 > --- a/drivers/i3c/master/mipi-i3c-hci/core.c > +++ b/drivers/i3c/master/mipi-i3c-hci/core.c > @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci) > if (ret) > return -ENXIO; > > - /* Disable all interrupts and allow all signal updates */ > + /* Disable all interrupts */ > reg_write(INTR_SIGNAL_ENABLE, 0x0); > - reg_write(INTR_STATUS_ENABLE, 0xffffffff); > + /* Allow signal updates relevant to IP versions 0.8 and beyond */ Nit: Only allow bit 31:10 signal update because Bit 0:9 is not neededed for DMA transfer when version >= 0.8 Bit 0:9 is not handled by pio driver when version < 0.8. Frank > + reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10)); > > /* Make sure our data ordering fits the host's */ > regval = reg_read(HC_CONTROL); > -- > 2.47.2 > > > -- > linux-i3c mailing list > linux-i3c@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-i3c
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index a71226d7ca59..e139d7e4d252 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci) if (ret) return -ENXIO; - /* Disable all interrupts and allow all signal updates */ + /* Disable all interrupts */ reg_write(INTR_SIGNAL_ENABLE, 0x0); - reg_write(INTR_STATUS_ENABLE, 0xffffffff); + /* Allow signal updates relevant to IP versions 0.8 and beyond */ + reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10)); /* Make sure our data ordering fits the host's */ regval = reg_read(HC_CONTROL);
Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the current driver code and not needed in DMA transfers. PIO transfers with v0.5 would require changes to both core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though. For these reasons don't enable signal updates from INTR_STATUS bits 9:0. This change gets rid of "unexpected INTR_STATUS" on old v0.5 IP version and is a no-op for later versions starting from v0.8. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> --- v2: Simplified the last sentence according to Frank Li's suggestion. --- drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)