[6.1.y-cip,00/85] soc: renesas: Add RZ/G3E support

Message ID	20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <yoshitake.kobayashi@toshiba.co.jp> ip: 52.101.229.29, mailfrom: tommaso.merciai.xr@bp.renesas.com) From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> CC: Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, tomm.merciai@gmail.com Subject: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support Date: Wed, 12 Mar 2025 12:21:37 +0100 Message-ID: <20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain
Series	soc: renesas: Add RZ/G3E support \| expand [6.1.y-cip,00/85] soc: renesas: Add RZ/G3E support [6.1.y-cip,01/85] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants [6.1.y-cip,02/85] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK [6.1.y-cip,03/85] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG [6.1.y-cip,04/85] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG [6.1.y-cip,05/85] clk: renesas: Add family-specific clock driver for RZ/V2H(P) [6.1.y-cip,06/85] clk: renesas: Add RZ/V2H(P) CPG driver [6.1.y-cip,07/85] clk: renesas: rzv2h: Add support for dynamic switching divider clocks [6.1.y-cip,08/85] clk: renesas: rzv2h: Add selective Runtime PM support for clocks [6.1.y-cip,09/85] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT [6.1.y-cip,10/85] clk: renesas: r9a09g057: Add CA55 core clocks [6.1.y-cip,11/85] clk: renesas: r9a09g057: Add clock and reset entries for ICU [6.1.y-cip,12/85] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets [6.1.y-cip,13/85] clk: renesas: rzv2h: Add MSTOP support [6.1.y-cip,14/85] clk: renesas: rzv2h: Add support for RZ/G3E SoC [6.1.y-cip,15/85] clk: renesas: r9a09g047: Add CA55 core clocks [6.1.y-cip,16/85] clk: renesas: r9a09g047: Add I2C clocks/resets [6.1.y-cip,17/85] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC [6.1.y-cip,18/85] arm64: dts: renesas: r9a09g047: Add OPP table [6.1.y-cip,19/85] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM [6.1.y-cip,20/85] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board [6.1.y-cip,21/85] soc: renesas: Add RZ/G3E (R9A09G047) config option [6.1.y-cip,22/85] arm64: defconfig: Enable R9A09G047 SoC [6.1.y-cip,23/85] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H [6.1.y-cip,24/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' pr… [6.1.y-cip,25/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object [6.1.y-cip,26/85] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC [6.1.y-cip,27/85] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain propert… [6.1.y-cip,28/85] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC [6.1.y-cip,29/85] pinctrl: renesas: rzg2l: Allow more bits for pin configuration [6.1.y-cip,30/85] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg [6.1.y-cip,31/85] pinctrl: renesas: rzg2l: Enable variable configuration for all [6.1.y-cip,32/85] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH [6.1.y-cip,33/85] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking [6.1.y-cip,34/85] pinctrl: renesas: rzg2l: Add function pointer for PMC register write [6.1.y-cip,35/85] pinctrl: renesas: rzg2l: Add function pointers for OEN register access [6.1.y-cip,36/85] pinctrl: renesas: rzg2l: Add support to configure slew-rate [6.1.y-cip,37/85] pinctrl: renesas: rzg2l: Add support for pull-up/down [6.1.y-cip,38/85] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_confi… [6.1.y-cip,39/85] pinctrl: renesas: rzg2l: Add support for custom parameters [6.1.y-cip,40/85] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() [6.1.y-cip,41/85] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC [6.1.y-cip,42/85] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide [6.1.y-cip,43/85] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) [6.1.y-cip,44/85] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file [6.1.y-cip,45/85] pinctrl: renesas: rzg2l: Reorganize variable configuration macro [6.1.y-cip,46/85] pinctrl: renesas: rzg2l: Clarify OEN read/write support [6.1.y-cip,47/85] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions [6.1.y-cip,48/85] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L [6.1.y-cip,49/85] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN [6.1.y-cip,50/85] pinctrl: renesas: rzg2l: Use dev_err_probe() [6.1.y-cip,51/85] mm/util: Introduce kmemdup_array() [6.1.y-cip,52/85] pinctrl: renesas: Switch to use kmemdup_array() [6.1.y-cip,53/85] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API [6.1.y-cip,54/85] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configur… [6.1.y-cip,55/85] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch… [6.1.y-cip,56/85] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX [6.1.y-cip,57/85] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() [6.1.y-cip,58/85] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs [6.1.y-cip,59/85] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger [6.1.y-cip,60/85] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper [6.1.y-cip,61/85] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table [6.1.y-cip,62/85] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC [6.1.y-cip,63/85] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E [6.1.y-cip,64/85] arm64: dts: renesas: r9a09g047: Add pincontrol node [6.1.y-cip,65/85] dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end [6.1.y-cip,66/85] dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' [6.1.y-cip,67/85] dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required [6.1.y-cip,68/85] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF sup… [6.1.y-cip,69/85] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif [6.1.y-cip,70/85] serial: sh-sci: describe locking requirements for invalidating RXDMA [6.1.y-cip,71/85] serial: sh-sci: Add support for RZ/V2H(P) SoC [6.1.y-cip,72/85] serial: sh-sci: Use plain struct copy in early_console_setup() [6.1.y-cip,73/85] serial: sh-sci: Check if TX data was written to device in .tx_empty() [6.1.y-cip,74/85] serial: sh-sci: Move runtime PM enable to sci_probe_single() [6.1.y-cip,75/85] serial: sh-sci: Clean sci_ports[0] after at earlycon exit [6.1.y-cip,76/85] serial: sh-sci: Increment the runtime usage counter for the earlycon device [6.1.y-cip,77/85] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol [6.1.y-cip,78/85] dt-bindings: i2c: renesas,riic: Document RZ/Five SoC [6.1.y-cip,79/85] dt-bindings: i2c: renesas,riic: Document R9A09G057 support [6.1.y-cip,80/85] dt-bindings: i2c: renesas,riic: Document the R9A08G045 support [6.1.y-cip,81/85] dt-bindings: i2c: renesas,riic: Document the R9A09G047 support [6.1.y-cip,82/85] i2c: riic: Introduce helper functions for I2C read/write operations [6.1.y-cip,83/85] i2c: riic: Pass register offsets and chip details as OF data [6.1.y-cip,84/85] i2c: riic: Add support for R9A09G057 SoC [6.1.y-cip,85/85] arm64: dts: renesas: r9a09g047: Add I2C nodes

Message ID

20250312112302.1605750-1-tommaso.merciai.xr@bp.renesas.com (mailing list archive)

Headers

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
CC: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	tomm.merciai@gmail.com
Subject: [PATCH 6.1.y-cip 00/85] soc: renesas: Add RZ/G3E support
Date: Wed, 12 Mar 2025 12:21:37 +0100
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Series

soc: renesas: Add RZ/G3E support | expand

Message

Tommaso Merciai March 12, 2025, 11:21 a.m. UTC

Dear All,

This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel.
All patches are cherry-picked from mainline kernel.

base commit: 8da62141b20b (tag: v6.1.129-cip38, linux-cip/linux-6.1.y-cip)

Thanks & Regards,
Tommaso


Andy Shevchenko (1):
  pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more
    suitable API

Biju Das (24):
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
  dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II
    EVK
  dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
  clk: renesas: rzv2h: Add MSTOP support
  clk: renesas: rzv2h: Add support for RZ/G3E SoC
  clk: renesas: r9a09g047: Add CA55 core clocks
  clk: renesas: r9a09g047: Add I2C clocks/resets
  arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC
  arm64: dts: renesas: r9a09g047: Add OPP table
  arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM
  arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK
    board
  soc: renesas: Add RZ/G3E (R9A09G047) config option
  arm64: defconfig: Enable R9A09G047 SoC
  dt-bindings: pinctrl: renesas: Add alpha-numerical port support for
    RZ/V2H
  dt-bindings: pinctrl: renesas: Document RZ/G3E SoC
  pinctrl: renesas: rzg2l: Use dev_err_probe()
  pinctrl: renesas: rzg2l: Fix missing return in
    rzg2l_pinctrl_register()
  pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table
  pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC
  arm64: dts: renesas: r9a09g047: Add pincontrol node
  dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif
  arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol
  dt-bindings: i2c: renesas,riic: Document the R9A09G047 support
  arm64: dts: renesas: r9a09g047: Add I2C nodes

Claudiu Beznea (5):
  serial: sh-sci: Check if TX data was written to device in .tx_empty()
  serial: sh-sci: Move runtime PM enable to sci_probe_single()
  serial: sh-sci: Clean sci_ports[0] after at earlycon exit
  serial: sh-sci: Increment the runtime usage counter for the earlycon
    device
  dt-bindings: i2c: renesas,riic: Document the R9A08G045 support

Fabrizio Castro (2):
  clk: renesas: r9a09g057: Add clock and reset entries for ICU
  pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX

Geert Uytterhoeven (1):
  serial: sh-sci: Use plain struct copy in early_console_setup()

Kartik (1):
  mm/util: Introduce kmemdup_array()

Lad Prabhakar (46):
  dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
  clk: renesas: Add family-specific clock driver for RZ/V2H(P)
  clk: renesas: Add RZ/V2H(P) CPG driver
  clk: renesas: rzv2h: Add support for dynamic switching divider clocks
  clk: renesas: rzv2h: Add selective Runtime PM support for clocks
  clk: renesas: r9a09g057: Add clock and reset entries for
    GTM/RIIC/SDHI/WDT
  clk: renesas: r9a09g057: Add CA55 core clocks
  clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and
    resets
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and
    'output-enable' properties
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the
    object
  dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open
    drain properties
  pinctrl: renesas: rzg2l: Allow more bits for pin configuration
  pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg
  pinctrl: renesas: rzg2l: Enable variable configuration for all
  pinctrl: renesas: rzg2l: Validate power registers for SD and ETH
  pinctrl: renesas: rzg2l: Add function pointer for PFC register locking
  pinctrl: renesas: rzg2l: Add function pointer for PMC register write
  pinctrl: renesas: rzg2l: Add function pointers for OEN register access
  pinctrl: renesas: rzg2l: Add support to configure slew-rate
  pinctrl: renesas: rzg2l: Add support for pull-up/down
  pinctrl: renesas: rzg2l: Pass pincontrol device to
    pinconf_generic_parse_dt_config()
  pinctrl: renesas: rzg2l: Add support for custom parameters
  pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc()
  pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC
  pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide
  pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use
    BIT(62)
  pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of
    the file
  pinctrl: renesas: rzg2l: Reorganize variable configuration macro
  pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support
    PIN_CFG_OEN
  pinctrl: renesas: rzg2l: Introduce single macro for digital noise
    filter configuration
  pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call
    outside of switch cases
  pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain
    outputs
  pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger
  pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell
    helper
  pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E
  dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end
  dt-bindings: serial: renesas,scif: Validate 'interrupts' and
    'interrupt-names'
  dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as
    required
  dt-bindings: serial: Add documentation for Renesas RZ/V2H(P)
    (R9A09G057) SCIF support
  serial: sh-sci: Add support for RZ/V2H(P) SoC
  dt-bindings: i2c: renesas,riic: Document RZ/Five SoC
  dt-bindings: i2c: renesas,riic: Document R9A09G057 support
  i2c: riic: Introduce helper functions for I2C read/write operations
  i2c: riic: Pass register offsets and chip details as OF data
  i2c: riic: Add support for R9A09G057 SoC

Paul Barker (3):
  pinctrl: renesas: rzg2l: Clarify OEN read/write support
  pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write
    functions
  pinctrl: renesas: rzg2l: Support output enable on RZ/G2L

Shen Lichuan (1):
  pinctrl: renesas: Switch to use kmemdup_array()

Wolfram Sang (1):
  serial: sh-sci: describe locking requirements for invalidating RXDMA

 .../devicetree/bindings/arm/renesas.yaml      |   17 +
 .../bindings/clock/renesas,rzv2h-cpg.yaml     |   83 ++
 .../devicetree/bindings/i2c/renesas,riic.yaml |   26 +-
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   61 +-
 .../bindings/serial/renesas,scif.yaml         |  141 +-
 arch/arm64/boot/dts/renesas/Makefile          |    2 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  387 ++++++
 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi |   18 +
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |   31 +
 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi |   13 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |   24 +
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |   28 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/renesas/Kconfig                   |   14 +
 drivers/clk/renesas/Makefile                  |    3 +
 drivers/clk/renesas/r9a09g047-cpg.c           |  150 ++
 drivers/clk/renesas/r9a09g057-cpg.c           |  280 ++++
 drivers/clk/renesas/rzv2h-cpg.c               |  999 ++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h               |  224 +++
 drivers/i2c/busses/i2c-riic.c                 |  125 +-
 drivers/pinctrl/renesas/Kconfig               |    1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 1229 +++++++++++++----
 drivers/pinctrl/renesas/pinctrl-rzv2m.c       |    3 +-
 drivers/pinctrl/renesas/pinctrl.c             |    3 +-
 drivers/soc/renesas/Kconfig                   |    5 +
 drivers/tty/serial/sh-sci.c                   |  160 ++-
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |   21 +
 .../dt-bindings/clock/renesas,r9a09g057-cpg.h |   21 +
 .../pinctrl/renesas,r9a09g047-pinctrl.h       |   41 +
 .../pinctrl/renesas,r9a09g057-pinctrl.h       |   31 +
 include/linux/serial_sci.h                    |    1 +
 include/linux/string.h                        |    1 +
 mm/util.c                                     |   17 +
 33 files changed, 3747 insertions(+), 414 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
 create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c
 create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h

Comments

Pavel Machek March 13, 2025, 10:51 a.m. UTC | #1

Hi!

> This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel.
> All patches are cherry-picked from mainline kernel.

85 patches, 3000+ lines of code. So we deserve so back story here:

What is RZ/G3E? Is it new generation of something? Is it used
somewhere?

Why is it important? Why is it important for -cip?

Does this add complete support? Or just enough to boot?

Is it in 6.12? If not, what will we do with 6.12-cip?

Do you have it in lab running tests somewhere? When was it released?
What was first mainline kernel to work there?

I'm curious, and, dunno, 50 lines of explanation what this is would
not be out of place for 3000 lines of patches.

Best regards,
								Pavel

Tommaso Merciai March 13, 2025, 11:53 a.m. UTC | #2

Hi Pavel,

Thanks for your comments.

On Thu, Mar 13, 2025 at 11:51:29AM +0100, Pavel Machek wrote:
> Hi!
> 
> > This series add support for RZ/G3E SoC to linux-6.1.y-cip kernel.
> > All patches are cherry-picked from mainline kernel.
> 
> 85 patches, 3000+ lines of code. So we deserve so back story here:

You are completely right.
Let me share with you some details:

> 
> What is RZ/G3E? Is it new generation of something? Is it used
> somewhere?

The RZ/G3E device is a general-purpose microprocessor with a quad-core CA-55,
single core CM-33, Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.

Here the first introduction to the kernel: [1]

> 
> Why is it important? Why is it important for -cip?
> 
> Does this add complete support? Or just enough to boot?

At the moment mainline supports only boot. So same backported here.
Going foward will add complete support.

> 
> Is it in 6.12? If not, what will we do with 6.12-cip?

We have a plan to port to 6.12, once cip releases 6.12 kernel.

> 
> Do you have it in lab running tests somewhere? When was it released?
> What was first mainline kernel to work there?

We have one on the lavalab, but is not up as mainline doesn't have ethernet support.
Eventually RZ/G3E board will be added in lava lab for testing once ethernet support added to mainline.

Does it answers all your questions?

> 
> I'm curious, and, dunno, 50 lines of explanation what this is would
> not be out of place for 3000 lines of patches.
> 
> Best regards,
> 								Pavel
> 
> -- 
> DENX Software Engineering GmbH,        Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[1] https://patchwork.kernel.org/project/linux-clk/cover/20241122124558.149827-1-biju.das.jz@bp.renesas.com/

Thanks & Regards,
Tommaso