| Message ID | 20250319214415.3086027-4-jonas@kwiboo.se (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: stmmac: dwmac-rk: Add GMAC support for RK3528 | expand |
On Wed, Mar 19, 2025 at 09:44:07PM +0000, Jonas Karlman wrote: > Rockchip RK3528 (and RV1106) has a different integrated PHY compared to > the integrated PHY on RK3228/RK3328. Current powerup/down operation is > not compatible with the integrated PHY found in these SoCs. > > Move the rk_gmac_integrated_phy_powerup/down functions to top of the > file to prepare for them to be called directly by a GMAC variant > specific powerup/down operation. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Andrew Lunn <andrew@lunn.ch> > +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) > +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) > + > +static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) > +{ > + if (priv->ops->integrated_phy_powerup) > + priv->ops->integrated_phy_powerup(priv); > + > + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); > + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); > + > + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); > + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); I know you are just moving code around.... Do you know what these MACPHY_ID are? I hope it is not what you get when you read PHY registers 2 and 3? Andrew
Hi Andrew, On 2025-03-19 23:39, Andrew Lunn wrote: > On Wed, Mar 19, 2025 at 09:44:07PM +0000, Jonas Karlman wrote: >> Rockchip RK3528 (and RV1106) has a different integrated PHY compared to >> the integrated PHY on RK3228/RK3328. Current powerup/down operation is >> not compatible with the integrated PHY found in these SoCs. >> >> Move the rk_gmac_integrated_phy_powerup/down functions to top of the >> file to prepare for them to be called directly by a GMAC variant >> specific powerup/down operation. >> >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > >> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) >> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) >> + >> +static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) >> +{ >> + if (priv->ops->integrated_phy_powerup) >> + priv->ops->integrated_phy_powerup(priv); >> + >> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); >> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); >> + >> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); >> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); > > I know you are just moving code around.... > > Do you know what these MACPHY_ID are? I hope it is not what you get > when you read PHY registers 2 and 3? I think it may be: GRF_MACPHY_CON2 15:0 macphy_id / PHY ID Number, macphy_cfg_phy_id[15:0] GRF_MACPHY_CON3 15:12 macphy_cfg_rev_nr / Manufacturer's Revision Number 11:6 macphy_model_nr / Manufacturer's Model Number 5:0 macphy_id / PHY ID Number, macphy_cfg_phy_id[21:16] and MACPHY_PHY_IDENTIFIER1 - Address: 02 15:0 PHY ID number / default:cfg_phy_id[15:0] MACPHY_PHY_IDENTIFIER2 - Address: 03 15:10 PHY ID number / default:cfg_phy_id[21:16] 9:4 Model number / default:cfg_model_nr[5:0] 3:0 Revision number / default:cfg_rev_nr[3:0] So likely what you get when you read PHY registers 2 and 3. Regards, Jonas > > Andrew
> > Do you know what these MACPHY_ID are? I hope it is not what you get > > when you read PHY registers 2 and 3? > > I think it may be: > > GRF_MACPHY_CON2 > 15:0 macphy_id / PHY ID Number, macphy_cfg_phy_id[15:0] > > GRF_MACPHY_CON3 > 15:12 macphy_cfg_rev_nr / Manufacturer's Revision Number > 11:6 macphy_model_nr / Manufacturer's Model Number > 5:0 macphy_id / PHY ID Number, macphy_cfg_phy_id[21:16] > > and > > MACPHY_PHY_IDENTIFIER1 - Address: 02 > 15:0 PHY ID number / default:cfg_phy_id[15:0] > > MACPHY_PHY_IDENTIFIER2 - Address: 03 > 15:10 PHY ID number / default:cfg_phy_id[21:16] > 9:4 Model number / default:cfg_model_nr[5:0] > 3:0 Revision number / default:cfg_rev_nr[3:0] > > So likely what you get when you read PHY registers 2 and 3. Ah: drivers/net/phy/rockchip.c #define INTERNAL_EPHY_ID 0x1234d400 However, it is not clear where the d4 come from. The problem here is the upper part should be an OUI from the vendor. I doubt rockchip actually own this OUI. They do actually have the MAC OUI: 10:DC:B6:90:00:00/28. I don't know if you can use a MAC OUI with a PHY ID? Andrew
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index dfb4668db4ee..0321befed0d3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -92,6 +92,50 @@ struct rk_priv_data { (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) +#define RK_GRF_MACPHY_CON0 0xb00 +#define RK_GRF_MACPHY_CON1 0xb04 +#define RK_GRF_MACPHY_CON2 0xb08 +#define RK_GRF_MACPHY_CON3 0xb0c + +#define RK_MACPHY_ENABLE GRF_BIT(0) +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) + +static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) +{ + if (priv->ops->integrated_phy_powerup) + priv->ops->integrated_phy_powerup(priv); + + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); + + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); + + if (priv->phy_reset) { + /* PHY needs to be disabled before trying to reset it */ + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); + if (priv->phy_reset) + reset_control_assert(priv->phy_reset); + usleep_range(10, 20); + if (priv->phy_reset) + reset_control_deassert(priv->phy_reset); + usleep_range(10, 20); + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); + msleep(30); + } +} + +static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) +{ + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); + if (priv->phy_reset) + reset_control_assert(priv->phy_reset); +} + #define PX30_GRF_GMAC_CON1 0x0904 /* PX30_GRF_GMAC_CON1 */ @@ -1463,50 +1507,6 @@ static const struct rk_gmac_ops rv1126_ops = { .set_rmii_speed = rv1126_set_rmii_speed, }; -#define RK_GRF_MACPHY_CON0 0xb00 -#define RK_GRF_MACPHY_CON1 0xb04 -#define RK_GRF_MACPHY_CON2 0xb08 -#define RK_GRF_MACPHY_CON3 0xb0c - -#define RK_MACPHY_ENABLE GRF_BIT(0) -#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) -#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) -#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) -#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) -#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) - -static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) -{ - if (priv->ops->integrated_phy_powerup) - priv->ops->integrated_phy_powerup(priv); - - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); - - regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); - regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); - - if (priv->phy_reset) { - /* PHY needs to be disabled before trying to reset it */ - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); - if (priv->phy_reset) - reset_control_assert(priv->phy_reset); - usleep_range(10, 20); - if (priv->phy_reset) - reset_control_deassert(priv->phy_reset); - usleep_range(10, 20); - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); - msleep(30); - } -} - -static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) -{ - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); - if (priv->phy_reset) - reset_control_assert(priv->phy_reset); -} - static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) { struct rk_priv_data *bsp_priv = plat->bsp_priv;
Rockchip RK3528 (and RV1106) has a different integrated PHY compared to the integrated PHY on RK3228/RK3328. Current powerup/down operation is not compatible with the integrated PHY found in these SoCs. Move the rk_gmac_integrated_phy_powerup/down functions to top of the file to prepare for them to be called directly by a GMAC variant specific powerup/down operation. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- Changes in v3: - No change Changes in v2: - New patch --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 88 +++++++++---------- 1 file changed, 44 insertions(+), 44 deletions(-)