| Message ID | 20250310-sm8750_ufs_master-v2-2-0dfdd6823161@quicinc.com |
|---|---|
| State | Accepted |
| Commit | b02cc9a176793b207e959701af1ec26222093b05 |
| Headers | show |
| Series | Add UFS support for SM8750 | expand |
Hi, On 10/03/2025 22:12, Melody Olvera wrote: > From: Nitin Rawat <quic_nitirawa@quicinc.com> > > Add SM8750 specific register layout and table configs. The serdes > TX RX register offset has changed for SM8750 and hence keep UFS > specific serdes offsets in a dedicated header file. > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 7 + > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 67 ++++++++ > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 180 ++++++++++++++++++++- > 3 files changed, 246 insertions(+), 8 deletions(-) > <snip> This change breaks UFS on the SM8550-HDK: [ 7.418161] qcom-qmp-ufs-phy 1d80000.phy: phy initialization timed-out [ 7.427021] phy phy-1d80000.phy.0: phy poweron failed --> -110 [ 7.493514] ufshcd-qcom 1d84000.ufshc: Enabling the controller failed ... GIT bisect points to: b02cc9a176793b207e959701af1ec26222093b05 is the first bad commit Author: Nitin Rawat <quic_nitirawa@quicinc.com> Date: Mon Mar 10 14:12:30 2025 -0700 phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 bisect log: git bisect start 'ff7f9b199e3f' 'v6.14-rc1' git bisect good 36c18c562846300d4e59f1a65008800b787f4fe4 git bisect good 85cf0293c3a75726e7bc54d3efdc5dc783debc07 git bisect good b2cd73e18cec75f917d14b9188f82a2fdef64ebe git bisect bad b247639d33ad16ea76797268fd0eef08d8027dfd git bisect good 9b3f2dfdad1cc0ab90a0fa371c8cbee08b2446e3 git bisect bad 8dc30c3e4cf8c4e370cf08bd09eb87b0deccd3de git bisect bad 100aeb03a437f30300894091627e4406605ee3cb git bisect bad b2a1a2ae7818c9d8da12bf7b1983c8b9f5fb712b git bisect good 8f831f272b4c89aa13b45bd010c2c18ad97a3f1b git bisect good e45cc62c23428eefbae18a9b4d88d10749741bdd git bisect bad ebf198f17b5ac967db6256f4083bbcbdcc2a3100 git bisect good 12185bc38f7667b1d895b2165a8a47335a4cf31b git bisect bad e46e59b77a9e6f322ef1ad08a8874211f389cf47 git bisect bad b02cc9a176793b207e959701af1ec26222093b05 CI run: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba-tester/-/jobs/229880#L1281 #regzbot introduced: b02cc9a17679 Neil
On 3/24/2025 11:40 PM, Neil Armstrong wrote: > Hi, > > On 10/03/2025 22:12, Melody Olvera wrote: >> From: Nitin Rawat <quic_nitirawa@quicinc.com> >> >> Add SM8750 specific register layout and table configs. The serdes >> TX RX register offset has changed for SM8750 and hence keep UFS >> specific serdes offsets in a dedicated header file. >> >> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> >> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 7 + >> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 67 ++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 180 +++++++++++ >> +++++++++- >> 3 files changed, 246 insertions(+), 8 deletions(-) >> > > <snip> > > This change breaks UFS on the SM8550-HDK: > > [ 7.418161] qcom-qmp-ufs-phy 1d80000.phy: phy initialization timed-out > [ 7.427021] phy phy-1d80000.phy.0: phy poweron failed --> -110 > [ 7.493514] ufshcd-qcom 1d84000.ufshc: Enabling the controller failed > ... Hi Neil, Thanks for testing and reporting. I did tested this patch on SM8750 MTP, SM8750 QRD, SM8650 MTP, SM8550 MTP and SM8850 QRD all of these have rate B and hence no issue. Unfortunately only SM8550 HDK platform which UFS4.0 and RateA couldn't get tested. As we know SM8550 with gear 5 only support rate A. I was applying rate B setting without checking for mode type. Since SM8550 is only platform which support only rate A with UFS4.0 . Hence this could be the issue. Meanwhile can you help test at your end with below change and let me if it resolves for you. I will also try at my end to test as well. ============================================================================= diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 45b3b792696e..b33e2e2b5014 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1754,7 +1754,8 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); } - qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); + if (qmp->mode == PHY_MODE_UFS_HS_B) + qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } ================================================================================= Thanks, Nitin > > GIT bisect points to: > b02cc9a176793b207e959701af1ec26222093b05 is the first bad commit > Author: Nitin Rawat <quic_nitirawa@quicinc.com> > Date: Mon Mar 10 14:12:30 2025 -0700 > > phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 > > bisect log: > git bisect start 'ff7f9b199e3f' 'v6.14-rc1' > git bisect good 36c18c562846300d4e59f1a65008800b787f4fe4 > git bisect good 85cf0293c3a75726e7bc54d3efdc5dc783debc07 > git bisect good b2cd73e18cec75f917d14b9188f82a2fdef64ebe > git bisect bad b247639d33ad16ea76797268fd0eef08d8027dfd > git bisect good 9b3f2dfdad1cc0ab90a0fa371c8cbee08b2446e3 > git bisect bad 8dc30c3e4cf8c4e370cf08bd09eb87b0deccd3de > git bisect bad 100aeb03a437f30300894091627e4406605ee3cb > git bisect bad b2a1a2ae7818c9d8da12bf7b1983c8b9f5fb712b > git bisect good 8f831f272b4c89aa13b45bd010c2c18ad97a3f1b > git bisect good e45cc62c23428eefbae18a9b4d88d10749741bdd > git bisect bad ebf198f17b5ac967db6256f4083bbcbdcc2a3100 > git bisect good 12185bc38f7667b1d895b2165a8a47335a4cf31b > git bisect bad e46e59b77a9e6f322ef1ad08a8874211f389cf47 > git bisect bad b02cc9a176793b207e959701af1ec26222093b05 > > CI run: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba- > tester/-/jobs/229880#L1281 > > #regzbot introduced: b02cc9a17679 > > Neil
Hi, On 25/03/2025 04:12, Nitin Rawat wrote: > > > On 3/24/2025 11:40 PM, Neil Armstrong wrote: >> Hi, >> >> On 10/03/2025 22:12, Melody Olvera wrote: >>> From: Nitin Rawat <quic_nitirawa@quicinc.com> >>> >>> Add SM8750 specific register layout and table configs. The serdes >>> TX RX register offset has changed for SM8750 and hence keep UFS >>> specific serdes offsets in a dedicated header file. >>> >>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> >>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> >>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> >>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >>> --- >>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 7 + >>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 67 ++++++++ >>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 180 +++++++++++ +++++++++- >>> 3 files changed, 246 insertions(+), 8 deletions(-) >>> >> >> <snip> >> >> This change breaks UFS on the SM8550-HDK: >> >> [ 7.418161] qcom-qmp-ufs-phy 1d80000.phy: phy initialization timed-out >> [ 7.427021] phy phy-1d80000.phy.0: phy poweron failed --> -110 >> [ 7.493514] ufshcd-qcom 1d84000.ufshc: Enabling the controller failed >> ... > > Hi Neil, > > Thanks for testing and reporting. > I did tested this patch on SM8750 MTP, SM8750 QRD, SM8650 MTP, SM8550 MTP and SM8850 QRD all of these have rate B and hence no issue. > > Unfortunately only SM8550 HDK platform which UFS4.0 and RateA couldn't get tested. As we know SM8550 with gear 5 only support rate A. > > I was applying rate B setting without checking for mode type. Since > SM8550 is only platform which support only rate A with UFS4.0 . Hence > this could be the issue. > > Meanwhile can you help test at your end with below change and let me if it resolves for you. I will also try at my end to test as well. > > ============================================================================= > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 45b3b792696e..b33e2e2b5014 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -1754,7 +1754,8 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg > qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); > } > > - qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); > + if (qmp->mode == PHY_MODE_UFS_HS_B) > + qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); > } > > ================================================================================= With this change the UFS works again. Thanks, Neil > > > Thanks, > Nitin > >> >> GIT bisect points to: >> b02cc9a176793b207e959701af1ec26222093b05 is the first bad commit >> Author: Nitin Rawat <quic_nitirawa@quicinc.com> >> Date: Mon Mar 10 14:12:30 2025 -0700 >> >> phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 >> >> bisect log: >> git bisect start 'ff7f9b199e3f' 'v6.14-rc1' >> git bisect good 36c18c562846300d4e59f1a65008800b787f4fe4 >> git bisect good 85cf0293c3a75726e7bc54d3efdc5dc783debc07 >> git bisect good b2cd73e18cec75f917d14b9188f82a2fdef64ebe >> git bisect bad b247639d33ad16ea76797268fd0eef08d8027dfd >> git bisect good 9b3f2dfdad1cc0ab90a0fa371c8cbee08b2446e3 >> git bisect bad 8dc30c3e4cf8c4e370cf08bd09eb87b0deccd3de >> git bisect bad 100aeb03a437f30300894091627e4406605ee3cb >> git bisect bad b2a1a2ae7818c9d8da12bf7b1983c8b9f5fb712b >> git bisect good 8f831f272b4c89aa13b45bd010c2c18ad97a3f1b >> git bisect good e45cc62c23428eefbae18a9b4d88d10749741bdd >> git bisect bad ebf198f17b5ac967db6256f4083bbcbdcc2a3100 >> git bisect good 12185bc38f7667b1d895b2165a8a47335a4cf31b >> git bisect bad e46e59b77a9e6f322ef1ad08a8874211f389cf47 >> git bisect bad b02cc9a176793b207e959701af1ec26222093b05 >> >> CI run: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba- tester/-/jobs/229880#L1281 >> >> #regzbot introduced: b02cc9a17679 >> >> Neil >
On 3/25/2025 1:04 PM, neil.armstrong@linaro.org wrote: > Hi, > > On 25/03/2025 04:12, Nitin Rawat wrote: >> >> >> On 3/24/2025 11:40 PM, Neil Armstrong wrote: >>> Hi, >>> >>> On 10/03/2025 22:12, Melody Olvera wrote: >>>> From: Nitin Rawat <quic_nitirawa@quicinc.com> >>>> >>>> Add SM8750 specific register layout and table configs. The serdes >>>> TX RX register offset has changed for SM8750 and hence keep UFS >>>> specific serdes offsets in a dedicated header file. >>>> >>>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> >>>> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> >>>> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> >>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 7 + >>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 67 ++++++++ >>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 180 +++++++++ >>>> ++ +++++++++- >>>> 3 files changed, 246 insertions(+), 8 deletions(-) >>>> >>> >>> <snip> >>> >>> This change breaks UFS on the SM8550-HDK: >>> >>> [ 7.418161] qcom-qmp-ufs-phy 1d80000.phy: phy initialization >>> timed-out >>> [ 7.427021] phy phy-1d80000.phy.0: phy poweron failed --> -110 >>> [ 7.493514] ufshcd-qcom 1d84000.ufshc: Enabling the controller failed >>> ... >> >> Hi Neil, >> >> Thanks for testing and reporting. >> I did tested this patch on SM8750 MTP, SM8750 QRD, SM8650 MTP, SM8550 >> MTP and SM8850 QRD all of these have rate B and hence no issue. >> >> Unfortunately only SM8550 HDK platform which UFS4.0 and RateA couldn't >> get tested. As we know SM8550 with gear 5 only support rate A. >> >> I was applying rate B setting without checking for mode type. Since >> SM8550 is only platform which support only rate A with UFS4.0 . Hence >> this could be the issue. >> >> Meanwhile can you help test at your end with below change and let me >> if it resolves for you. I will also try at my end to test as well. >> >> ============================================================================= >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/ >> qualcomm/phy-qcom-qmp-ufs.c >> index 45b3b792696e..b33e2e2b5014 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> @@ -1754,7 +1754,8 @@ static void qmp_ufs_init_registers(struct >> qmp_ufs *qmp, const struct qmp_phy_cfg >> qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); >> } >> >> - qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); >> + if (qmp->mode == PHY_MODE_UFS_HS_B) >> + qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); >> } >> >> ================================================================================= > > With this change the UFS works again. Thanks Neil for quick revert. I'll raise the official change. Regards, nitin > > Thanks, > Neil > >> >> >> Thanks, >> Nitin >> >>> >>> GIT bisect points to: >>> b02cc9a176793b207e959701af1ec26222093b05 is the first bad commit >>> Author: Nitin Rawat <quic_nitirawa@quicinc.com> >>> Date: Mon Mar 10 14:12:30 2025 -0700 >>> >>> phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750 >>> >>> bisect log: >>> git bisect start 'ff7f9b199e3f' 'v6.14-rc1' >>> git bisect good 36c18c562846300d4e59f1a65008800b787f4fe4 >>> git bisect good 85cf0293c3a75726e7bc54d3efdc5dc783debc07 >>> git bisect good b2cd73e18cec75f917d14b9188f82a2fdef64ebe >>> git bisect bad b247639d33ad16ea76797268fd0eef08d8027dfd >>> git bisect good 9b3f2dfdad1cc0ab90a0fa371c8cbee08b2446e3 >>> git bisect bad 8dc30c3e4cf8c4e370cf08bd09eb87b0deccd3de >>> git bisect bad 100aeb03a437f30300894091627e4406605ee3cb >>> git bisect bad b2a1a2ae7818c9d8da12bf7b1983c8b9f5fb712b >>> git bisect good 8f831f272b4c89aa13b45bd010c2c18ad97a3f1b >>> git bisect good e45cc62c23428eefbae18a9b4d88d10749741bdd >>> git bisect bad ebf198f17b5ac967db6256f4083bbcbdcc2a3100 >>> git bisect good 12185bc38f7667b1d895b2165a8a47335a4cf31b >>> git bisect bad e46e59b77a9e6f322ef1ad08a8874211f389cf47 >>> git bisect bad b02cc9a176793b207e959701af1ec26222093b05 >>> >>> CI run: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba- >>> tester/-/jobs/229880#L1281 >>> >>> #regzbot introduced: b02cc9a17679 >>> >>> Neil >> >
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h index 328c6c0b0b09ae4ff5bf14e846772e6d0f31ce5a..258f3d30742e8bc93a56aee3431d6e227a6bb791 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h @@ -86,4 +86,11 @@ #define QSERDES_V6_COM_CMN_STATUS 0x1d0 #define QSERDES_V6_COM_C_READY_STATUS 0x1f8 +#define QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG 0x268 +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270 +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274 +#define QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1 0x278 +#define QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c +#define QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h new file mode 100644 index 0000000000000000000000000000000000000000..3f0522492f857ebfededd39748ec849678069bf4 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_ + +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28 +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c +#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108 + +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 +#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28 +#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 +#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58 +#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xc4 +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xd4 +#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xdc +#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xf0 +#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xf4 +#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178 +#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1b4 +#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1cc +#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1d4 +#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1f0 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230 +#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234 +#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248 +#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254 +#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26c +#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274 +#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27c +#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28c +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29c +#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2a0 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2a8 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2ac +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2b0 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2b4 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2b8 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2bc +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2c0 +#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2c4 +#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348 +#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380 +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index d964bdfe870029226482f264c78a27d0ec43bf2b..45b3b792696e9ed17ca9dedcf8e71202d27e86a2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -31,6 +31,7 @@ #include "phy-qcom-qmp-pcs-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" /* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) @@ -949,6 +950,124 @@ static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), }; +static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; + +static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17), +}; + +static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30), + QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77), +}; + +static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), +}; + +static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), +}; + +static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -1523,6 +1642,45 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { .regs = ufsphy_v6_regs_layout, }; +static const struct qmp_phy_cfg sm8750_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets_v6, + .max_supported_gear = UFS_HS_G5, + + .tbls = { + .serdes = sm8750_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes), + .tx = sm8750_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx), + .rx = sm8750_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx), + .pcs = sm8750_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs), + }, + + .tbls_hs_b = { + .pcs = sm8750_ufsphy_hs_b_pcs, + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs), + }, + + .tbls_hs_overlay[0] = { + .pcs = sm8750_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs), + .max_gear = UFS_HS_G4, + }, + .tbls_hs_overlay[1] = { + .pcs = sm8650_ufsphy_g5_pcs, + .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), + .max_gear = UFS_HS_G5, + }, + + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = ufsphy_v6_regs_layout, + +}; + static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) { void __iomem *serdes = qmp->serdes; @@ -1578,23 +1736,25 @@ static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cf return ret; } +static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) +{ + qmp_ufs_serdes_init(qmp, tbls); + qmp_ufs_lanes_init(qmp, tbls); + qmp_ufs_pcs_init(qmp, tbls); +} + static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) { int i; - qmp_ufs_serdes_init(qmp, &cfg->tbls); - qmp_ufs_lanes_init(qmp, &cfg->tbls); - qmp_ufs_pcs_init(qmp, &cfg->tbls); + qmp_ufs_init_all(qmp, &cfg->tbls); i = qmp_ufs_get_gear_overlay(qmp, cfg); if (i >= 0) { - qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]); - qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]); - qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]); + qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); } - if (qmp->mode == PHY_MODE_UFS_HS_B) - qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); + qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); } static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -2061,7 +2221,11 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { }, { .compatible = "qcom,sm8650-qmp-ufs-phy", .data = &sm8650_ufsphy_cfg, + }, { + .compatible = "qcom,sm8750-qmp-ufs-phy", + .data = &sm8750_ufsphy_cfg, }, + { }, }; MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);