[v3,3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready

Commit Message

Hongxing Zhu March 28, 2025, 3:02 a.m. UTC

ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
or PERST# De-assertion

When the auxiliary power is not available, the controller cannot exit from
L23 Ready with beacon or PERST# de-assertion when main power is not
removed.

Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.

Signed-off-by: Richard Zhu <[e-mail]>
Reviewed-by: Frank Li <[e-mail]>
---
 drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Manivannan Sadhasivam April 2, 2025, 7:07 a.m. UTC | #1

On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
> or PERST# De-assertion

Is it possible to share the link to the erratum?

> 
> When the auxiliary power is not available, the controller cannot exit from
> L23 Ready with beacon or PERST# de-assertion when main power is not
> removed.
> 

I don't understand how the presence of Vaux affects the controller. Same goes
for PERST# deassertion. How does that relate to Vaux? Is this erratum for
a specific endpoint behavior?

- Mani

Hongxing Zhu April 2, 2025, 7:59 a.m. UTC | #2

> -----Original Message-----
> From: Manivannan Sadhasivam <[e-mail]>
> Sent: 2025年4月2日 15:08
> To: Hongxing Zhu <[e-mail]>
> Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]
> Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> ready
> 
> On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through
> > Beacon or PERST# De-assertion
> 
> Is it possible to share the link to the erratum?
> 
Sorry, the erratum document isn't ready to be published yet.
> >
> > When the auxiliary power is not available, the controller cannot exit
> > from
> > L23 Ready with beacon or PERST# de-assertion when main power is not
> > removed.
> >
> 
> I don't understand how the presence of Vaux affects the controller. Same goes
> for PERST# deassertion. How does that relate to Vaux? Is this erratum for a
> specific endpoint behavior?
IMHO I don't know the exact details of the power supplies in this IP design.
Refer to my guess , maybe the beacon detect or wake-up logic in designs is
 relied on the status of SYS_AUX_PWR_DET signals in this case.

Best Regards
Richard Zhu
> 
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்

Manivannan Sadhasivam April 2, 2025, 3:17 p.m. UTC | #3

On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Manivannan Sadhasivam <[e-mail]>
> > Sent: 2025年4月2日 15:08
> > To: Hongxing Zhu <[e-mail]>
> > Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]
> > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> > ready
> > 
> > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through
> > > Beacon or PERST# De-assertion
> > 
> > Is it possible to share the link to the erratum?
> > 
> Sorry, the erratum document isn't ready to be published yet.
> > >
> > > When the auxiliary power is not available, the controller cannot exit
> > > from
> > > L23 Ready with beacon or PERST# de-assertion when main power is not
> > > removed.
> > >
> > 
> > I don't understand how the presence of Vaux affects the controller. Same goes
> > for PERST# deassertion. How does that relate to Vaux? Is this erratum for a
> > specific endpoint behavior?
> IMHO I don't know the exact details of the power supplies in this IP design.
> Refer to my guess , maybe the beacon detect or wake-up logic in designs is
>  relied on the status of SYS_AUX_PWR_DET signals in this case.

Can you please try to get more details? I couldn't understand the errata.

- Mani

Hongxing Zhu April 3, 2025, 3:22 a.m. UTC | #4

> -----Original Message-----
> From: Manivannan Sadhasivam <[e-mail]>
> Sent: 2025年4月2日 23:18
> To: Hongxing Zhu <[e-mail]>
> Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]
> Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> ready
> 
> On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Manivannan Sadhasivam <[e-mail]>
> > > Sent: 2025年4月2日 15:08
> > > To: Hongxing Zhu <[e-mail]>
> > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > not exit L23 ready
> > >
> > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > Through Beacon or PERST# De-assertion
> > >
> > > Is it possible to share the link to the erratum?
> > >
> > Sorry, the erratum document isn't ready to be published yet.
> > > >
> > > > When the auxiliary power is not available, the controller cannot
> > > > exit from
> > > > L23 Ready with beacon or PERST# de-assertion when main power is
> > > > not removed.
> > > >
> > >
> > > I don't understand how the presence of Vaux affects the controller.
> > > Same goes for PERST# deassertion. How does that relate to Vaux? Is
> > > this erratum for a specific endpoint behavior?
> > IMHO I don't know the exact details of the power supplies in this IP design.
> > Refer to my guess , maybe the beacon detect or wake-up logic in
> > designs is  relied on the status of SYS_AUX_PWR_DET signals in this case.
> 
> Can you please try to get more details? I couldn't understand the errata.
> 
Sure. Will contact designer and try to get more details.

Best Regards
Richard Zhu
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்

Hongxing Zhu April 8, 2025, 3:02 a.m. UTC | #5

> -----Original Message-----
> From: Hongxing Zhu
> Sent: 2025年4月3日 11:23
> To: Manivannan Sadhasivam <[e-mail]>
> Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]
> Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit
> L23 ready
> 
> > -----Original Message-----
> > From: Manivannan Sadhasivam <[e-mail]>
> > Sent: 2025年4月2日 23:18
> > To: Hongxing Zhu <[e-mail]>
> > Cc: Frank Li <[e-mail]>; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]
> > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not
> > exit L23 ready
> >
> > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > Sent: 2025年4月2日 15:08
> > > > To: Hongxing Zhu <[e-mail]>
> > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]
> > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > not exit L23 ready
> > > >
> > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > > Through Beacon or PERST# De-assertion
> > > >
> > > > Is it possible to share the link to the erratum?
> > > >
> > > Sorry, the erratum document isn't ready to be published yet.
> > > > >
> > > > > When the auxiliary power is not available, the controller cannot
> > > > > exit from
> > > > > L23 Ready with beacon or PERST# de-assertion when main power is
> > > > > not removed.
> > > > >
> > > >
> > > > I don't understand how the presence of Vaux affects the controller.
> > > > Same goes for PERST# deassertion. How does that relate to Vaux? Is
> > > > this erratum for a specific endpoint behavior?
> > > IMHO I don't know the exact details of the power supplies in this IP design.
> > > Refer to my guess , maybe the beacon detect or wake-up logic in
> > > designs is  relied on the status of SYS_AUX_PWR_DET signals in this case.
> >
> > Can you please try to get more details? I couldn't understand the errata.
> >
> Sure. Will contact designer and try to get more details.
Hi Mani:
Get some information from designs, the internal design logic is relied on the
 status of SYS_AUX_PWR_DET signal to handle the low power stuff.
So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW workaround.

Best Regards
Richard Zhu

> 
> Best Regards
> Richard Zhu
> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்

Manivannan Sadhasivam April 9, 2025, 4:43 p.m. UTC | #6

On Tue, Apr 08, 2025 at 03:02:42AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Hongxing Zhu
> > Sent: 2025年4月3日 11:23
> > To: Manivannan Sadhasivam <[e-mail]>
> > Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]
> > Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit
> > L23 ready
> > 
> > > -----Original Message-----
> > > From: Manivannan Sadhasivam <[e-mail]>
> > > Sent: 2025年4月2日 23:18
> > > To: Hongxing Zhu <[e-mail]>
> > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]
> > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not
> > > exit L23 ready
> > >
> > > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > > -----Original Message-----
> > > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > > Sent: 2025年4月2日 15:08
> > > > > To: Hongxing Zhu <[e-mail]>
> > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail]
> > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > > not exit L23 ready
> > > > >
> > > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > > > Through Beacon or PERST# De-assertion
> > > > >
> > > > > Is it possible to share the link to the erratum?
> > > > >
> > > > Sorry, the erratum document isn't ready to be published yet.
> > > > > >
> > > > > > When the auxiliary power is not available, the controller cannot
> > > > > > exit from
> > > > > > L23 Ready with beacon or PERST# de-assertion when main power is
> > > > > > not removed.
> > > > > >
> > > > >
> > > > > I don't understand how the presence of Vaux affects the controller.
> > > > > Same goes for PERST# deassertion. How does that relate to Vaux? Is
> > > > > this erratum for a specific endpoint behavior?
> > > > IMHO I don't know the exact details of the power supplies in this IP design.
> > > > Refer to my guess , maybe the beacon detect or wake-up logic in
> > > > designs is  relied on the status of SYS_AUX_PWR_DET signals in this case.
> > >
> > > Can you please try to get more details? I couldn't understand the errata.
> > >
> > Sure. Will contact designer and try to get more details.
> Hi Mani:
> Get some information from designs, the internal design logic is relied on the
>  status of SYS_AUX_PWR_DET signal to handle the low power stuff.
> So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW workaround.
> 

Ok. So due to the errata, when the link enters L23 Ready state, it cannot
transition to L3 when Vaux is not available. And the workaround requires setting
SYS_AUX_PWR_DET bit?

IIUC, the issue here is that the controller is not able to detect the presence
of Vaux in the L23 Ready state. So it relies on the SYS_AUX_PWR_DET bit. But
even in that case, how would you support the endpoint *with* Vaux?

- Mani

Hongxing Zhu April 10, 2025, 2:45 a.m. UTC | #7

> -----Original Message-----
> From: Manivannan Sadhasivam <[e-mail]>
> Sent: 2025年4月10日 0:44
> To: Hongxing Zhu <[e-mail]>
> Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]
> Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> ready
> 
> On Tue, Apr 08, 2025 at 03:02:42AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Hongxing Zhu
> > > Sent: 2025年4月3日 11:23
> > > To: Manivannan Sadhasivam <[e-mail]>
> > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > not exit
> > > L23 ready
> > >
> > > > -----Original Message-----
> > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > Sent: 2025年4月2日 23:18
> > > > To: Hongxing Zhu <[e-mail]>
> > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]
> > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > not exit L23 ready
> > > >
> > > > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > > > -----Original Message-----
> > > > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > > > Sent: 2025年4月2日 15:08
> > > > > > To: Hongxing Zhu <[e-mail]>
> > > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail];
> > > > > > [e-mail]; [e-mail]
> > > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe
> > > > > > may not exit L23 ready
> > > > > >
> > > > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > > > > Through Beacon or PERST# De-assertion
> > > > > >
> > > > > > Is it possible to share the link to the erratum?
> > > > > >
> > > > > Sorry, the erratum document isn't ready to be published yet.
> > > > > > >
> > > > > > > When the auxiliary power is not available, the controller
> > > > > > > cannot exit from
> > > > > > > L23 Ready with beacon or PERST# de-assertion when main power
> > > > > > > is not removed.
> > > > > > >
> > > > > >
> > > > > > I don't understand how the presence of Vaux affects the controller.
> > > > > > Same goes for PERST# deassertion. How does that relate to
> > > > > > Vaux? Is this erratum for a specific endpoint behavior?
> > > > > IMHO I don't know the exact details of the power supplies in this IP
> design.
> > > > > Refer to my guess , maybe the beacon detect or wake-up logic in
> > > > > designs is  relied on the status of SYS_AUX_PWR_DET signals in this
> case.
> > > >
> > > > Can you please try to get more details? I couldn't understand the errata.
> > > >
> > > Sure. Will contact designer and try to get more details.
> > Hi Mani:
> > Get some information from designs, the internal design logic is relied
> > on the  status of SYS_AUX_PWR_DET signal to handle the low power stuff.
> > So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW workaround.
> >
> 
> Ok. So due to the errata, when the link enters L23 Ready state, it cannot
> transition to L3 when Vaux is not available. And the workaround requires setting
> SYS_AUX_PWR_DET bit?
> 
Refer to the description of this errata, it just mentions the exist from
 L23 Ready state.
Yes, the workaround requires setting SYS_AUX_PWR_DET bit to 1b'1.

> IIUC, the issue here is that the controller is not able to detect the presence of
> Vaux in the L23 Ready state. So it relies on the SYS_AUX_PWR_DET bit. But even
> in that case, how would you support the endpoint *with* Vaux?
> 
This errata is only applied for i.MX95 dual PCIe mode controller.
The Vaux is not present for i.MX95 PCIe EP mode either.

Best Regards
Richard Zhu
> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்

Manivannan Sadhasivam April 13, 2025, 3:38 p.m. UTC | #8

On Thu, Apr 10, 2025 at 02:45:51AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Manivannan Sadhasivam <[e-mail]>
> > Sent: 2025年4月10日 0:44
> > To: Hongxing Zhu <[e-mail]>
> > Cc: Frank Li <[e-mail]>; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]
> > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> > ready
> > 
> > On Tue, Apr 08, 2025 at 03:02:42AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Hongxing Zhu
> > > > Sent: 2025年4月3日 11:23
> > > > To: Manivannan Sadhasivam <[e-mail]>
> > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]
> > > > Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > not exit
> > > > L23 ready
> > > >
> > > > > -----Original Message-----
> > > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > > Sent: 2025年4月2日 23:18
> > > > > To: Hongxing Zhu <[e-mail]>
> > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail]
> > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > > > not exit L23 ready
> > > > >
> > > > > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > > > > -----Original Message-----
> > > > > > > From: Manivannan Sadhasivam <[e-mail]>
> > > > > > > Sent: 2025年4月2日 15:08
> > > > > > > To: Hongxing Zhu <[e-mail]>
> > > > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > > > [e-mail]; [e-mail];
> > > > > > > [e-mail]; [e-mail];
> > > > > > > [e-mail]; [e-mail];
> > > > > > > [e-mail];
> > > > > > > [e-mail]; [e-mail]
> > > > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe
> > > > > > > may not exit L23 ready
> > > > > > >
> > > > > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > > > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
> > > > > > > > Through Beacon or PERST# De-assertion
> > > > > > >
> > > > > > > Is it possible to share the link to the erratum?
> > > > > > >
> > > > > > Sorry, the erratum document isn't ready to be published yet.
> > > > > > > >
> > > > > > > > When the auxiliary power is not available, the controller
> > > > > > > > cannot exit from
> > > > > > > > L23 Ready with beacon or PERST# de-assertion when main power
> > > > > > > > is not removed.
> > > > > > > >
> > > > > > >
> > > > > > > I don't understand how the presence of Vaux affects the controller.
> > > > > > > Same goes for PERST# deassertion. How does that relate to
> > > > > > > Vaux? Is this erratum for a specific endpoint behavior?
> > > > > > IMHO I don't know the exact details of the power supplies in this IP
> > design.
> > > > > > Refer to my guess , maybe the beacon detect or wake-up logic in
> > > > > > designs is  relied on the status of SYS_AUX_PWR_DET signals in this
> > case.
> > > > >
> > > > > Can you please try to get more details? I couldn't understand the errata.
> > > > >
> > > > Sure. Will contact designer and try to get more details.
> > > Hi Mani:
> > > Get some information from designs, the internal design logic is relied
> > > on the  status of SYS_AUX_PWR_DET signal to handle the low power stuff.
> > > So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW workaround.
> > >
> > 
> > Ok. So due to the errata, when the link enters L23 Ready state, it cannot
> > transition to L3 when Vaux is not available. And the workaround requires setting
> > SYS_AUX_PWR_DET bit?
> > 
> Refer to the description of this errata, it just mentions the exist from
>  L23 Ready state.

Exiting from L23 Ready == entering L2/L3. And since you mentioned that Vaux is
not available, it is definitely entering L3.

> Yes, the workaround requires setting SYS_AUX_PWR_DET bit to 1b'1.
> 
> > IIUC, the issue here is that the controller is not able to detect the presence of
> > Vaux in the L23 Ready state. So it relies on the SYS_AUX_PWR_DET bit. But even
> > in that case, how would you support the endpoint *with* Vaux?
> > 
> This errata is only applied for i.MX95 dual PCIe mode controller.
> The Vaux is not present for i.MX95 PCIe EP mode either.
> 

First of all, does the controller really know whether Vaux is supplied to the
endpoint or not? AFAIK, it is up to the board designers to route Vaux and only
endpoint should care about it.

I still feel that this specific erratum is for fixing the issue with some
endpoints where Vaux is not supplied and the link doesn't exit L23 Ready. Again,
what would be the behavior if Vaux is supplied to the endpoint? You cannot just
say that the controller doesn't support Vaux, which is not a valid statement
IMO.

- Mani

Hongxing Zhu April 14, 2025, 3:15 a.m. UTC | #9

> -----Original Message-----
> From: Manivannan Sadhasivam <[e-mail]>
> Sent: 2025年4月13日 23:39
> To: Hongxing Zhu <[e-mail]>
> Cc: Frank Li <[e-mail]>; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]
> Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit
> L23 ready
> 
> On Thu, Apr 10, 2025 at 02:45:51AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Manivannan Sadhasivam <[e-mail]>
> > > Sent: 2025年4月10日 0:44
> > > To: Hongxing Zhu <[e-mail]>
> > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may
> > > not exit L23 ready
> > >
> > > On Tue, Apr 08, 2025 at 03:02:42AM +0000, Hongxing Zhu wrote:
> > > > > -----Original Message-----
> > > > > From: Hongxing Zhu
> > > > > Sent: 2025年4月3日 11:23
> > > > > To: Manivannan Sadhasivam <[e-mail]>
> > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail]; [e-mail];
> > > > > [e-mail];
> > > > > [e-mail]; [e-mail]
> > > > > Subject: RE: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe
> > > > > may not exit
> > > > > L23 ready
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Manivannan Sadhasivam
> <[e-mail]>
> > > > > > Sent: 2025年4月2日 23:18
> > > > > > To: Hongxing Zhu <[e-mail]>
> > > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail]; [e-mail];
> > > > > > [e-mail];
> > > > > > [e-mail]; [e-mail]
> > > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe
> > > > > > may not exit L23 ready
> > > > > >
> > > > > > On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > > > > > > > -----Original Message-----
> > > > > > > > From: Manivannan Sadhasivam
> > > > > > > > <[e-mail]>
> > > > > > > > Sent: 2025年4月2日 15:08
> > > > > > > > To: Hongxing Zhu <[e-mail]>
> > > > > > > > Cc: Frank Li <[e-mail]>; [e-mail];
> > > > > > > > [e-mail]; [e-mail]; [e-mail];
> > > > > > > > [e-mail]; [e-mail];
> > > > > > > > [e-mail]; [e-mail];
> > > > > > > > [e-mail]; [e-mail];
> > > > > > > > [e-mail];
> > > > > > > > [e-mail]; [e-mail]
> > > > > > > > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95
> > > > > > > > PCIe may not exit L23 ready
> > > > > > > >
> > > > > > > > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > > > > > > > ERR051624: The Controller Without Vaux Cannot Exit L23
> > > > > > > > > Ready Through Beacon or PERST# De-assertion
> > > > > > > >
> > > > > > > > Is it possible to share the link to the erratum?
> > > > > > > >
> > > > > > > Sorry, the erratum document isn't ready to be published yet.
> > > > > > > > >
> > > > > > > > > When the auxiliary power is not available, the
> > > > > > > > > controller cannot exit from
> > > > > > > > > L23 Ready with beacon or PERST# de-assertion when main
> > > > > > > > > power is not removed.
> > > > > > > > >
> > > > > > > >
> > > > > > > > I don't understand how the presence of Vaux affects the
> controller.
> > > > > > > > Same goes for PERST# deassertion. How does that relate to
> > > > > > > > Vaux? Is this erratum for a specific endpoint behavior?
> > > > > > > IMHO I don't know the exact details of the power supplies in
> > > > > > > this IP
> > > design.
> > > > > > > Refer to my guess , maybe the beacon detect or wake-up logic
> > > > > > > in designs is  relied on the status of SYS_AUX_PWR_DET
> > > > > > > signals in this
> > > case.
> > > > > >
> > > > > > Can you please try to get more details? I couldn't understand the
> errata.
> > > > > >
> > > > > Sure. Will contact designer and try to get more details.
> > > > Hi Mani:
> > > > Get some information from designs, the internal design logic is
> > > > relied on the  status of SYS_AUX_PWR_DET signal to handle the low
> power stuff.
> > > > So, the SYS_AUX_PWR_DET is required to be 1b'1 in the SW
> workaround.
> > > >
> > >
> > > Ok. So due to the errata, when the link enters L23 Ready state, it
> > > cannot transition to L3 when Vaux is not available. And the
> > > workaround requires setting SYS_AUX_PWR_DET bit?
> > >
> > Refer to the description of this errata, it just mentions the exist
> > from
> >  L23 Ready state.
> 
> Exiting from L23 Ready == entering L2/L3. And since you mentioned that Vaux
> is not available, it is definitely entering L3.
> 
> > Yes, the workaround requires setting SYS_AUX_PWR_DET bit to 1b'1.
> >
> > > IIUC, the issue here is that the controller is not able to detect
> > > the presence of Vaux in the L23 Ready state. So it relies on the
> > > SYS_AUX_PWR_DET bit. But even in that case, how would you support the
> endpoint *with* Vaux?
> > >
> > This errata is only applied for i.MX95 dual PCIe mode controller.
> > The Vaux is not present for i.MX95 PCIe EP mode either.
> >
> 
> First of all, does the controller really know whether Vaux is supplied to the
> endpoint or not? AFAIK, it is up to the board designers to route Vaux and only
> endpoint should care about it.
> 
> I still feel that this specific erratum is for fixing the issue with some endpoints
> where Vaux is not supplied and the link doesn't exit L23 Ready. Again, what
> would be the behavior if Vaux is supplied to the endpoint? You cannot just say
> that the controller doesn't support Vaux, which is not a valid statement IMO.
> 
Sorry, I miss-understand the question you posted in the previous reply.
I get the following answer from designers when the Vaux is supplied to the
 remote endpoint. Hope it can get ride of your concerns.
Q:
How about the situations when remote partner has the Vaux present?
For example, i.MX95 PCIe used as RC, and a endpoint device with one Vaux
 present is connected to i.MX95 PCIe RC.

A:
" As per my understanding it should work irrespective of vaux presence in remote partner."

Best Regards
Richard Zhu

> - Mani
> 
> --
> மணிவண்ணன் சதாசிவம்

Patch

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6051b3b5928f..82402e52eff2 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -48,6 +48,8 @@ 
 #define IMX95_PCIE_SS_RW_REG_0			0xf0
 #define IMX95_PCIE_REF_CLKEN			BIT(23)
 #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
+#define IMX95_PCIE_SS_RW_REG_1			0xf4
+#define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
 
 #define IMX95_PE0_GEN_CTRL_1			0x1050
 #define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
@@ -227,6 +229,19 @@  static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	/*
+	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
+	 * Through Beacon or PERST# De-assertion
+	 *
+	 * When the auxiliary power is not available, the controller
+	 * cannot exit from L23 Ready with beacon or PERST# de-assertion
+	 * when main power is not removed.
+	 *
+	 * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
+	 */
+	regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+			IMX95_PCIE_SYS_AUX_PWR_DET);
+
 	regmap_update_bits(imx_pcie->iomuxc_gpr,
 			IMX95_PCIE_SS_RW_REG_0,
 			IMX95_PCIE_PHY_CR_PARA_SEL,