diff mbox series

clk: sophgo: Fixes Coccinelle/coccicheck warnings reported by do_div.cocci.

Message ID tencent_D5D35C992B70843CF70F5533E49717D24906@qq.com (mailing list archive)
State Under Review
Headers show
Series clk: sophgo: Fixes Coccinelle/coccicheck warnings reported by do_div.cocci. | expand

Commit Message

xiaopeitux@foxmail.com April 7, 2025, 3:21 a.m. UTC
From: Pei Xiao <xiaopei01@kylinos.cn>

cocci warnings:
    drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING:
    do_div() does a 64-by-32 division, please consider using div64_ul
    instead.

    drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING:
    do_div() does a 64-by-32 division, please consider using div64_u64
    instead.

replace do_div() with div64_*() which doesn't implicitly cast the divisor.

Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
---
 drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Inochi Amaoto April 7, 2025, 3:55 a.m. UTC | #1
On Mon, Apr 07, 2025 at 11:21:46AM +0800, xiaopeitux@foxmail.com wrote:
> From: Pei Xiao <xiaopei01@kylinos.cn>
> 
> cocci warnings:
>     drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING:
>     do_div() does a 64-by-32 division, please consider using div64_ul
>     instead.
> 
>     drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING:
>     do_div() does a 64-by-32 division, please consider using div64_u64
>     instead.
> 
> replace do_div() with div64_*() which doesn't implicitly cast the divisor.
> 
> Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
> ---
>  drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

LGTM.

Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Chen Wang April 7, 2025, 9:01 a.m. UTC | #2
On 2025/4/7 11:21, xiaopeitux@foxmail.com wrote:
> From: Pei Xiao <xiaopei01@kylinos.cn>
>
> cocci warnings:
>      drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING:
>      do_div() does a 64-by-32 division, please consider using div64_ul
>      instead.
>
>      drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING:
>      do_div() does a 64-by-32 division, please consider using div64_u64
>      instead.
>
> replace do_div() with div64_*() which doesn't implicitly cast the divisor.

hi Pei,I'm not sure if you discovered this issue via the test robot, see 
this: https://lore.kernel.org/lkml/202504051456.niworhgJ-lkp@intel.com/. 
If so, please add its Reported-by signature in the commit as required. 
Otherwise please ignore my input.

As per this patch itself, LGTM.

Reviewed-by: Chen Wang <wangchen20@iscas.ac.cn>


>
> Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
> ---
>   drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
> index 1537f4f05860..e5fb0bb7ac4f 100644
> --- a/drivers/clk/sophgo/clk-sg2042-pll.c
> +++ b/drivers/clk/sophgo/clk-sg2042-pll.c
> @@ -155,7 +155,7 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
>   
>   	numerator = (u64)parent_rate * ctrl_table.fbdiv;
>   	denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> -	do_div(numerator, denominator);
> +	numerator =  div64_u64(numerator, denominator);
>   	return numerator;
>   }
>   
> @@ -212,7 +212,7 @@ static int sg2042_pll_get_postdiv_1_2(unsigned long rate,
>   	tmp0 *= fbdiv;
>   
>   	/* ((prate/REFDIV) x FBDIV)/rate and result save to tmp0 */
> -	do_div(tmp0, rate);
> +	tmp0 = div64_ul(tmp0, rate);
>   
>   	/* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */
>   	if (tmp0 <= 7) {
diff mbox series

Patch

diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
index 1537f4f05860..e5fb0bb7ac4f 100644
--- a/drivers/clk/sophgo/clk-sg2042-pll.c
+++ b/drivers/clk/sophgo/clk-sg2042-pll.c
@@ -155,7 +155,7 @@  static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
 
 	numerator = (u64)parent_rate * ctrl_table.fbdiv;
 	denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
-	do_div(numerator, denominator);
+	numerator =  div64_u64(numerator, denominator);
 	return numerator;
 }
 
@@ -212,7 +212,7 @@  static int sg2042_pll_get_postdiv_1_2(unsigned long rate,
 	tmp0 *= fbdiv;
 
 	/* ((prate/REFDIV) x FBDIV)/rate and result save to tmp0 */
-	do_div(tmp0, rate);
+	tmp0 = div64_ul(tmp0, rate);
 
 	/* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */
 	if (tmp0 <= 7) {