| Message ID | 20250407142359.1398410-6-chaitanya.kumar.borah@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/xe/display: Program double buffered LUT registers | expand |
On Mon, Apr 07, 2025 at 07:53:53PM +0530, Chaitanya Kumar Borah wrote: > A DSB buffer which will be used for GOSUB execution does not need > the DEWAKE mechanism but still need to be 64 bit aligned. Add helper > to finish preparation of a dsb buffer to be executed with GOSUB > instruction. > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++ > drivers/gpu/drm/i915/display/intel_dsb.h | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c > index 2cda6fc7857b..bffa02a0442c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb, > intel_dsb_align_tail(dsb); > } > > +void intel_dsb_gosub_finish(struct intel_dsb *dsb) > +{ > + intel_dsb_align_tail(dsb); There is one more w/a listd that may require us to do something like:: /* "All subroutines called by the GOSUB instruction must end with a cacheline of NOPs" */ intel_dsb_noop(8); > + > + intel_dsb_buffer_flush_map(&dsb->dsb_buf); > +} > + > void intel_dsb_finish(struct intel_dsb *dsb) > { > struct intel_crtc *crtc = dsb->crtc; > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h > index 8b2cf0a7b7e6..6900acd603b8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.h > +++ b/drivers/gpu/drm/i915/display/intel_dsb.h > @@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, > enum intel_dsb_id dsb_id, > unsigned int max_cmds); > void intel_dsb_finish(struct intel_dsb *dsb); > +void intel_dsb_gosub_finish(struct intel_dsb *dsb); > void intel_dsb_cleanup(struct intel_dsb *dsb); > void intel_dsb_reg_write(struct intel_dsb *dsb, > i915_reg_t reg, u32 val); > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2cda6fc7857b..bffa02a0442c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb, intel_dsb_align_tail(dsb); } +void intel_dsb_gosub_finish(struct intel_dsb *dsb) +{ + intel_dsb_align_tail(dsb); + + intel_dsb_buffer_flush_map(&dsb->dsb_buf); +} + void intel_dsb_finish(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 8b2cf0a7b7e6..6900acd603b8 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); +void intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
A DSB buffer which will be used for GOSUB execution does not need the DEWAKE mechanism but still need to be 64 bit aligned. Add helper to finish preparation of a dsb buffer to be executed with GOSUB instruction. Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> --- drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 1 + 2 files changed, 8 insertions(+)