| Message ID | 20250410095158.8966-1-yiru.zhang@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] Add ETE devarch condition in etm4_init_iomem_access | expand |
Hi, Please stop using the unusual title format of [PATCH}[Patch v3] - use the git command line options to ensure the format is e.g. [PATCH v3] What is the reason that your device cannot use the system instructions to access the ETE? Using a memory interface, if implemented, is only recommended for external debuggers, or on systems where the implementation of system register access is not working. On Thu, 10 Apr 2025 at 10:52, yiru zhang <yiru.zhang@mediatek.com> wrote: > > Due to ETE supported, so add ETE devarch condition in etm4_init_iomem_access. > > Signed-off-by: yiru zhang <yiru.zhang@mediatek.com> > Reported-by: kernel test robot <lkp@intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202504101759.7Ls0Uy4o-lkp@intel.com/ > > v1->v2: use switch case way > v2->v3: clean build warning > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 2b8f10463840..4002a2823fd0 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1135,11 +1135,15 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, > * with MMIO. But we cannot touch the OSLK until we are > * sure this is an ETM. So rely only on the TRCDEVARCH. > */ > - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) { > - pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); > + switch (devarch & ETM_DEVARCH_ID_MASK) { > + case ETM_DEVARCH_ETMv4x_ARCH: > + case ETM_DEVARCH_ETE_ARCH: > + break; > + default: > + pr_warn_once("Unknown ETM architecture: 0x%lx\n", > + devarch & ETM_DEVARCH_ID_MASK); > return false; > } > - > drvdata->arch = etm_devarch_to_arch(devarch); > *csa = CSDEV_ACCESS_IOMEM(drvdata->base); > return true; > -- > 2.46.0 > Otherwise - Reviewed-by: Mike Leach <mike.leach@linaro.org>
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2b8f10463840..4002a2823fd0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1135,11 +1135,15 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, * with MMIO. But we cannot touch the OSLK until we are * sure this is an ETM. So rely only on the TRCDEVARCH. */ - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) { - pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); + switch (devarch & ETM_DEVARCH_ID_MASK) { + case ETM_DEVARCH_ETMv4x_ARCH: + case ETM_DEVARCH_ETE_ARCH: + break; + default: + pr_warn_once("Unknown ETM architecture: 0x%lx\n", + devarch & ETM_DEVARCH_ID_MASK); return false; } - drvdata->arch = etm_devarch_to_arch(devarch); *csa = CSDEV_ACCESS_IOMEM(drvdata->base); return true;
Due to ETE supported, so add ETE devarch condition in etm4_init_iomem_access. Signed-off-by: yiru zhang <yiru.zhang@mediatek.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202504101759.7Ls0Uy4o-lkp@intel.com/ v1->v2: use switch case way v2->v3: clean build warning --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)