| Message ID | 1744267805-119602-1-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dw-rockchip: Add system PM support | expand |
On 4/10/25 15:50, Shawn Lin wrote: > +static int rockchip_pcie_suspend(struct device *dev) > +{ > + struct rockchip_pcie *rockchip = dev_get_drvdata(dev); > + struct dw_pcie *pci = &rockchip->pci; > + int ret; > + > + rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY); > + > + ret = dw_pcie_suspend_noirq(pci); > + if (ret) { > + dev_err(dev, "failed to suspend\n"); > + return ret; > + } > + > + rockchip_pcie_phy_deinit(rockchip); > + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); > + reset_control_assert(rockchip->rst); > + if (rockchip->vpcie3v3) > + regulator_disable(rockchip->vpcie3v3); > + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); > + > + return 0; > +} This function needs a __maybe_unused in its declaration, otherwise, you get a compilation warning when PM is not enabled. static int __maybe_unused rockchip_pcie_suspend(struct device *dev) > +static int rockchip_pcie_resume(struct device *dev) Same here too.
在 2025/04/11 星期五 10:02, Damien Le Moal 写道: > On 4/10/25 15:50, Shawn Lin wrote: >> +static int rockchip_pcie_suspend(struct device *dev) >> +{ >> + struct rockchip_pcie *rockchip = dev_get_drvdata(dev); >> + struct dw_pcie *pci = &rockchip->pci; >> + int ret; >> + >> + rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY); >> + >> + ret = dw_pcie_suspend_noirq(pci); >> + if (ret) { >> + dev_err(dev, "failed to suspend\n"); >> + return ret; >> + } >> + >> + rockchip_pcie_phy_deinit(rockchip); >> + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); >> + reset_control_assert(rockchip->rst); >> + if (rockchip->vpcie3v3) >> + regulator_disable(rockchip->vpcie3v3); >> + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); >> + >> + return 0; >> +} > > This function needs a __maybe_unused in its declaration, otherwise, you get a > compilation warning when PM is not enabled. > > static int __maybe_unused rockchip_pcie_suspend(struct device *dev) > > Emm.. I don't see any host drivers with system PM support under drivers/pci/controller/ adds these :) #grep suspend drivers/pci/controller/ -rn | grep __maybe_unused | wc -l 0 Anyway, will fix it. >> +static int rockchip_pcie_resume(struct device *dev) > > Same here too. > >
On 4/11/25 11:26, Shawn Lin wrote: > 在 2025/04/11 星期五 10:02, Damien Le Moal 写道: >> On 4/10/25 15:50, Shawn Lin wrote: >>> +static int rockchip_pcie_suspend(struct device *dev) >>> +{ >>> + struct rockchip_pcie *rockchip = dev_get_drvdata(dev); >>> + struct dw_pcie *pci = &rockchip->pci; >>> + int ret; >>> + >>> + rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY); >>> + >>> + ret = dw_pcie_suspend_noirq(pci); >>> + if (ret) { >>> + dev_err(dev, "failed to suspend\n"); >>> + return ret; >>> + } >>> + >>> + rockchip_pcie_phy_deinit(rockchip); >>> + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); >>> + reset_control_assert(rockchip->rst); >>> + if (rockchip->vpcie3v3) >>> + regulator_disable(rockchip->vpcie3v3); >>> + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); >>> + >>> + return 0; >>> +} >> >> This function needs a __maybe_unused in its declaration, otherwise, you get a >> compilation warning when PM is not enabled. >> >> static int __maybe_unused rockchip_pcie_suspend(struct device *dev) >> >> > > Emm.. I don't see any host drivers with system PM support under > drivers/pci/controller/ adds these :) > > #grep suspend drivers/pci/controller/ -rn | grep __maybe_unused | wc -l > 0 > > Anyway, will fix it. If you do not add __maybe_unused, you get: CC drivers/pci/controller/dwc/pcie-dw-rockchip.o drivers/pci/controller/dwc/pcie-dw-rockchip.c:761:12: warning: ‘rockchip_pcie_resume’ defined but not used [-Wunused-function] 761 | static int rockchip_pcie_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ drivers/pci/controller/dwc/pcie-dw-rockchip.c:737:12: warning: ‘rockchip_pcie_suspend’ defined but not used [-Wunused-function] 737 | static int rockchip_pcie_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ You do not get this for other controllers because they use NOIRQ_SYSTEM_SLEEP_PM_OPS() to set the PM ops. Your patch uses SET_NOIRQ_SYSTEM_SLEEP_PM_OPS() which is defined as: #ifdef CONFIG_PM_SLEEP #define SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) \ NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) #else #define SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(suspend_fn, resume_fn) #endif So unlike using directly NOIRQ_SYSTEM_SLEEP_PM_OPS(), the functions names are actually never used when CONFIG_PM_SLEEP is not enabled. So the fix is to do like other controllers and use NOIRQ_SYSTEM_SLEEP_PM_OPS() or use __maybe_unused.
Hi Shawn, kernel test robot noticed the following build warnings: [auto build test WARNING on pci/next] [also build test WARNING on pci/for-linus linus/master v6.15-rc1 next-20250410] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Lin/PCI-dw-rockchip-Add-system-PM-support/20250410-145426 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/1744267805-119602-1-git-send-email-shawn.lin%40rock-chips.com patch subject: [PATCH] PCI: dw-rockchip: Add system PM support config: x86_64-buildonly-randconfig-001-20250411 (https://download.01.org/0day-ci/archive/20250411/202504111625.Eds7X9BC-lkp@intel.com/config) compiler: gcc-11 (Debian 11.3.0-12) 11.3.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250411/202504111625.Eds7X9BC-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202504111625.Eds7X9BC-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/pci/controller/dwc/pcie-dw-rockchip.c:749:12: warning: 'rockchip_pcie_resume' defined but not used [-Wunused-function] 749 | static int rockchip_pcie_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ >> drivers/pci/controller/dwc/pcie-dw-rockchip.c:725:12: warning: 'rockchip_pcie_suspend' defined but not used [-Wunused-function] 725 | static int rockchip_pcie_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ vim +/rockchip_pcie_resume +749 drivers/pci/controller/dwc/pcie-dw-rockchip.c 724 > 725 static int rockchip_pcie_suspend(struct device *dev) 726 { 727 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 728 struct dw_pcie *pci = &rockchip->pci; 729 int ret; 730 731 rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY); 732 733 ret = dw_pcie_suspend_noirq(pci); 734 if (ret) { 735 dev_err(dev, "failed to suspend\n"); 736 return ret; 737 } 738 739 rockchip_pcie_phy_deinit(rockchip); 740 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); 741 reset_control_assert(rockchip->rst); 742 if (rockchip->vpcie3v3) 743 regulator_disable(rockchip->vpcie3v3); 744 gpiod_set_value_cansleep(rockchip->rst_gpio, 0); 745 746 return 0; 747 } 748 > 749 static int rockchip_pcie_resume(struct device *dev) 750 { 751 struct rockchip_pcie *rockchip = dev_get_drvdata(dev); 752 struct dw_pcie *pci = &rockchip->pci; 753 int ret; 754 755 reset_control_assert(rockchip->rst); 756 757 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); 758 if (ret) { 759 dev_err(dev, "clock init failed\n"); 760 goto err_clk; 761 } 762 763 if (rockchip->vpcie3v3) { 764 ret = regulator_enable(rockchip->vpcie3v3); 765 if (ret) 766 goto err_power; 767 } 768 769 ret = phy_init(rockchip->phy); 770 if (ret) { 771 dev_err(dev, "fail to init phy\n"); 772 goto err_phy_init; 773 } 774 775 ret = phy_power_on(rockchip->phy); 776 if (ret) { 777 dev_err(dev, "fail to power on phy\n"); 778 goto err_phy_on; 779 } 780 781 reset_control_deassert(rockchip->rst); 782 783 rockchip_pcie_writel_apb(rockchip, HIWORD_UPDATE(0xffff, rockchip->intx), 784 PCIE_CLIENT_INTR_MASK_LEGACY); 785 786 rockchip_pcie_ltssm_enable_control_mode(rockchip, PCIE_CLIENT_RC_MODE); 787 rockchip_pcie_unmask_dll_indicator(rockchip); 788 789 ret = dw_pcie_resume_noirq(pci); 790 if (ret) { 791 dev_err(dev, "fail to resume\n"); 792 goto err_resume; 793 } 794 795 return 0; 796 797 err_resume: 798 phy_power_off(rockchip->phy); 799 err_phy_on: 800 phy_exit(rockchip->phy); 801 err_phy_init: 802 if (rockchip->vpcie3v3) 803 regulator_disable(rockchip->vpcie3v3); 804 err_power: 805 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); 806 err_clk: 807 reset_control_deassert(rockchip->rst); 808 return ret; 809 } 810
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 56acfea..229c606 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -21,6 +21,7 @@ #include <linux/regmap.h> #include <linux/reset.h> +#include "../../pci.h" #include "pcie-designware.h" /* @@ -37,8 +38,14 @@ #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 #define PCIE_CLIENT_INTR_MASK_MISC 0x24 +#define PCIE_CLIENT_POWER 0x2c +#define PCIE_CLIENT_MSG_GEN 0x34 +#define PME_READY_ENTER_L23 BIT(3) +#define PME_TURN_OFF (BIT(4) | BIT(20)) +#define PME_TO_ACK (BIT(9) | BIT(25)) #define PCIE_SMLH_LINKUP BIT(16) #define PCIE_RDLH_LINKUP BIT(17) #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) @@ -63,6 +70,7 @@ struct rockchip_pcie { struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; struct irq_domain *irq_domain; + u32 intx; const struct rockchip_pcie_of_data *data; }; @@ -159,6 +167,13 @@ static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); } +static u32 rockchip_pcie_get_pure_ltssm(struct dw_pcie *pci) +{ + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + + return rockchip_pcie_get_ltssm(rockchip) & PCIE_LTSSM_STATUS_MASK; +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -248,8 +263,42 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + struct device *dev = rockchip->pci.dev; + int ret; + u32 status; + + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) + dev_warn(dev, "Failed to send PME_Turn_Off\n"); + + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX, + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); + + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX); + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER, + status, status & PME_READY_ENTER_L23, + PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) + dev_err(dev, "Failed to get ready to enter L23 message\n"); +} + static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { .init = rockchip_pcie_host_init, + .pme_turn_off = rockchip_pcie_pme_turn_off, }; /* @@ -430,6 +479,7 @@ static const struct dw_pcie_ops dw_pcie_ops = { .link_up = rockchip_pcie_link_up, .start_link = rockchip_pcie_start_link, .stop_link = rockchip_pcie_stop_link, + .get_ltssm = rockchip_pcie_get_pure_ltssm, }; static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) @@ -489,13 +539,32 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) return IRQ_HANDLED; } +static void rockchip_pcie_ltssm_enable_control_mode(struct rockchip_pcie *rockchip, u32 mode) +{ + u32 val; + + /* LTSSM enable control mode */ + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CONTROL); +} + +static void rockchip_pcie_unmask_dll_indicator(struct rockchip_pcie *rockchip) +{ + u32 val; + + /* unmask DLL up/down indicator */ + val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED, 0); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { struct device *dev = &pdev->dev; struct dw_pcie_rp *pp; int irq, ret; - u32 val; if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST)) return -ENODEV; @@ -512,12 +581,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, return ret; } - /* LTSSM enable control mode */ - val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, - PCIE_CLIENT_GENERAL_CONTROL); + rockchip_pcie_ltssm_enable_control_mode(rockchip, PCIE_CLIENT_RC_MODE); pp = &rockchip->pci.pp; pp->ops = &rockchip_pcie_host_ops; @@ -529,9 +593,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, return ret; } - /* unmask DLL up/down indicator */ - val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED, 0); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC); + rockchip_pcie_unmask_dll_indicator(rockchip); return ret; } @@ -558,12 +620,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev, return ret; } - /* LTSSM enable control mode */ - val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, - PCIE_CLIENT_GENERAL_CONTROL); + rockchip_pcie_ltssm_enable_control_mode(rockchip, PCIE_CLIENT_EP_MODE); rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; rockchip->pci.ep.page_size = SZ_64K; @@ -677,6 +734,92 @@ static int rockchip_pcie_probe(struct platform_device *pdev) return ret; } +static int rockchip_pcie_suspend(struct device *dev) +{ + struct rockchip_pcie *rockchip = dev_get_drvdata(dev); + struct dw_pcie *pci = &rockchip->pci; + int ret; + + rockchip->intx = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MASK_LEGACY); + + ret = dw_pcie_suspend_noirq(pci); + if (ret) { + dev_err(dev, "failed to suspend\n"); + return ret; + } + + rockchip_pcie_phy_deinit(rockchip); + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + reset_control_assert(rockchip->rst); + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); + + return 0; +} + +static int rockchip_pcie_resume(struct device *dev) +{ + struct rockchip_pcie *rockchip = dev_get_drvdata(dev); + struct dw_pcie *pci = &rockchip->pci; + int ret; + + reset_control_assert(rockchip->rst); + + ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); + if (ret) { + dev_err(dev, "clock init failed\n"); + goto err_clk; + } + + if (rockchip->vpcie3v3) { + ret = regulator_enable(rockchip->vpcie3v3); + if (ret) + goto err_power; + } + + ret = phy_init(rockchip->phy); + if (ret) { + dev_err(dev, "fail to init phy\n"); + goto err_phy_init; + } + + ret = phy_power_on(rockchip->phy); + if (ret) { + dev_err(dev, "fail to power on phy\n"); + goto err_phy_on; + } + + reset_control_deassert(rockchip->rst); + + rockchip_pcie_writel_apb(rockchip, HIWORD_UPDATE(0xffff, rockchip->intx), + PCIE_CLIENT_INTR_MASK_LEGACY); + + rockchip_pcie_ltssm_enable_control_mode(rockchip, PCIE_CLIENT_RC_MODE); + rockchip_pcie_unmask_dll_indicator(rockchip); + + ret = dw_pcie_resume_noirq(pci); + if (ret) { + dev_err(dev, "fail to resume\n"); + goto err_resume; + } + + return 0; + +err_resume: + phy_power_off(rockchip->phy); +err_phy_on: + phy_exit(rockchip->phy); +err_phy_init: + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); +err_power: + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); +err_clk: + reset_control_deassert(rockchip->rst); + return ret; +} + static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { .mode = DW_PCIE_RC_TYPE, }; @@ -707,11 +850,17 @@ static const struct of_device_id rockchip_pcie_of_match[] = { {}, }; +static const struct dev_pm_ops rockchip_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend, + rockchip_pcie_resume) +}; + static struct platform_driver rockchip_pcie_driver = { .driver = { .name = "rockchip-dw-pcie", .of_match_table = rockchip_pcie_of_match, .suppress_bind_attrs = true, + .pm = &rockchip_pcie_pm_ops, }, .probe = rockchip_pcie_probe, };
This patch adds system PM support for Rockchip platforms by adding .pme_turn_off and .get_ltssm hook and tries to reuse possible exist code. It's tested on RK3576 EVB1 board with Some NVMes and PCIe-2-SATA/XHCI devices. And check the PCIe protocol analyzer to make sure the L2 process fits the spec. [ 1.541394] nvme nvme0: missing or invalid SUBNQN field. [ 1.548755] nvme nvme0: allocated 64 MiB host memory buffer (16 segments). [ 1.562235] nvme nvme0: 8/0/0 default/read/poll queues [ 1.563930] nvme nvme0: Ignoring bogus Namespace Identifiers [ 58.443602] PM: suspend entry (deep) [ 58.444005] Filesystems sync: 0.000 seconds [ 58.445542] Freezing user space processes [ 58.447096] Freezing user space processes completed (elapsed 0.001 seconds) [ 58.447718] OOM killer disabled. [ 58.448008] Freezing remaining freezable tasks [ 58.449080] Freezing remaining freezable tasks completed (elapsed 0.000 seconds) ... [ 58.797070] rockchip-dw-pcie 22400000.pcie: PCIe Gen.2 x1 link up [ 58.835953] OOM killer enabled. [ 58.836262] Restarting tasks ... done. [ 58.839241] random: crng reseeded on system resumption [ 58.840679] PM: suspend exit [ 59.500036] nvme nvme0: 8/0/0 default/read/poll queues [ 59.500909] nvme nvme0: Ignoring bogus Namespace Identifiers 1000+0 records in 1000+0 records out real 0m 5.51s user 0m 0.00s sys 0m 0.71s Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 181 +++++++++++++++++++++++--- 1 file changed, 165 insertions(+), 16 deletions(-)