diff mbox series

[RFC,5/5] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2

Message ID 20250413085806.8544-6-linux@fw-web.de
State RFC
Headers show
Series Add mt7988 XS-PHY | expand

Commit Message

Frank Wunderlich April 13, 2025, 8:58 a.m. UTC 
From: Frank Wunderlich <frank-w@public-files.de>

First usb and third pcie controller on mt7988 need a xs-phy to work
properly.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

Comments

AngeloGioacchino Del Regno April 14, 2025, 10:27 a.m. UTC | #1 
Il 13/04/25 10:58, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> First usb and third pcie controller on mt7988 need a xs-phy to work
> properly.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>   arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++
>   1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index 88b56a24efca..10525d977007 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -334,6 +334,8 @@ usb@11190000 {
>   				 <&infracfg CLK_INFRA_133M_USB_HCK>,
>   				 <&infracfg CLK_INFRA_USB_XHCI>;
>   			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
> +			phys = <&xphyu2port0 PHY_TYPE_USB2>,
> +			       <&xphyu3port0 PHY_TYPE_USB3>;
>   			status = "disabled";
>   		};
>   
> @@ -398,6 +400,9 @@ pcie2: pcie@11280000 {
>   			pinctrl-0 = <&pcie2_pins>;
>   			status = "disabled";
>   
> +			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
> +			phy-names = "pcie-phy";
> +
>   			#interrupt-cells = <1>;
>   			interrupt-map-mask = <0 0 0 0x7>;
>   			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
> @@ -548,6 +553,40 @@ tphyu3port0: usb-phy@11c50700 {
>   			};
>   		};
>   
> +		topmisc: power-controller@11d10000 {
> +			compatible = "mediatek,mt7988-topmisc", "syscon",
> +				     "mediatek,mt7988-power-controller";
> +			reg = <0 0x11d10000 0 0x10000>;
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		xs-phy@11e10000 {

That shall be just "phy@addr"

> +			compatible = "mediatek,mt7988-xsphy",
> +				     "mediatek,xsphy";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			xphyu2port0: usb-phy@11e10000 {

Perhaps just u2port0/u3port0 like done on the other MediaTek SoC DTs is better
for consistency :-)

Cheers!

> +				reg = <0 0x11e10000 0 0x400>;
> +				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			xphyu3port0: usb-phy@11e13000 {
> +				reg = <0 0x11e13400 0 0x500>;
> +				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +				mediatek,syscon-type = <&topmisc 0x218 0>;
> +			};
> +		};
> +
>   		clock-controller@11f40000 {
>   			compatible = "mediatek,mt7988-xfi-pll";
>   			reg = <0 0x11f40000 0 0x1000>;
Frank Wunderlich April 14, 2025, 10:57 a.m. UTC | #2 
Am 14. April 2025 12:27:30 MESZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:
>Il 13/04/25 10:58, Frank Wunderlich ha scritto:
>> From: Frank Wunderlich <frank-w@public-files.de>

>> +		xs-phy@11e10000 {
>
>That shall be just "phy@addr"

Ok

>> +			compatible = "mediatek,mt7988-xsphy",
>> +				     "mediatek,xsphy";
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +			status = "disabled";
>> +
>> +			xphyu2port0: usb-phy@11e10000 {
>
>Perhaps just u2port0/u3port0 like done on the other MediaTek SoC DTs is better
>for consistency :-)

Mt7988 also have a tphy where we have it named tphyu3port. Leaving this imho would increase confusion.

>Cheers!
>


regards Frank
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 88b56a24efca..10525d977007 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -334,6 +334,8 @@  usb@11190000 {
 				 <&infracfg CLK_INFRA_133M_USB_HCK>,
 				 <&infracfg CLK_INFRA_USB_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+			phys = <&xphyu2port0 PHY_TYPE_USB2>,
+			       <&xphyu3port0 PHY_TYPE_USB3>;
 			status = "disabled";
 		};
 
@@ -398,6 +400,9 @@  pcie2: pcie@11280000 {
 			pinctrl-0 = <&pcie2_pins>;
 			status = "disabled";
 
+			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+			phy-names = "pcie-phy";
+
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
@@ -548,6 +553,40 @@  tphyu3port0: usb-phy@11c50700 {
 			};
 		};
 
+		topmisc: power-controller@11d10000 {
+			compatible = "mediatek,mt7988-topmisc", "syscon",
+				     "mediatek,mt7988-power-controller";
+			reg = <0 0x11d10000 0 0x10000>;
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		xs-phy@11e10000 {
+			compatible = "mediatek,mt7988-xsphy",
+				     "mediatek,xsphy";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			xphyu2port0: usb-phy@11e10000 {
+				reg = <0 0x11e10000 0 0x400>;
+				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			xphyu3port0: usb-phy@11e13000 {
+				reg = <0 0x11e13400 0 0x500>;
+				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+				mediatek,syscon-type = <&topmisc 0x218 0>;
+			};
+		};
+
 		clock-controller@11f40000 {
 			compatible = "mediatek,mt7988-xfi-pll";
 			reg = <0 0x11f40000 0 0x1000>;