@@ -1,5 +1,6 @@
obj-y += lib/
obj-$(CONFIG_MMU) += mmu/
+obj-$(CONFIG_MPU) += mpu/
obj-$(CONFIG_EARLY_PRINTK) += debug.o
obj-y += domctl.o
new file mode 100644
@@ -0,0 +1 @@
+obj-y += head.o
new file mode 100644
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Start-of-day code for an Armv8-R-AArch32 MPU system.
+ */
+
+#include <asm/arm32/macros.h>
+#include <asm/arm32/sysregs.h>
+#include <asm/cpregs.h>
+#include <asm/mpu.h>
+#include <asm/mpu/regions.inc>
+#include <asm/page.h>
+
+/*
+ * Set up the memory attribute type tables and enable EL2 MPU and data cache.
+ * If the Background region is enabled, then the MPU uses the default memory
+ * map as the Background region for generating the memory
+ * attributes when MPU is disabled.
+ * Since the default memory map of the Armv8-R AArch32 architecture is
+ * IMPLEMENTATION DEFINED, we intend to turn off the Background region here.
+ *
+ * Clobbers r0
+ */
+FUNC_LOCAL(enable_mpu)
+ /* Set up memory attribute type tables */
+ mov_w r0, MAIR0VAL
+ mcr CP32(r0, HMAIR0)
+ mov_w r0, MAIR1VAL
+ mcr CP32(r0, HMAIR1)
+
+ mrc CP32(r0, HSCTLR)
+ bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */
+ orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */
+ orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */
+ mcr CP32(r0, HSCTLR)
+ isb
+
+ ret
+END(enable_mpu)
+
+/*
+ * Maps the various sections of Xen (described in xen.lds.S) as different MPU
+ * regions.
+ *
+ * Clobbers r0 - r5
+ *
+ */
+FUNC(enable_boot_cpu_mm)
+ /* Get the number of regions specified in MPUIR_EL2 */
+ mrc CP32(r5, MPUIR_EL2)
+ and r5, r5, #NUM_MPU_REGIONS_MASK
+
+ /* x0: region sel */
+ mov r0, #0
+ /* Xen text section. */
+ mov_w r1, _stext
+ mov_w r2, _etext
+ prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR
+
+ /* Xen read-only data section. */
+ mov_w r1, _srodata
+ mov_w r2, _erodata
+ prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_RO_PRBAR
+
+ /* Xen read-only after init and data section. (RW data) */
+ mov_w r1, __ro_after_init_start
+ mov_w r2, __init_begin
+ prepare_xen_region r0, r1, r2, r3, r4, r5
+
+ /* Xen code section. */
+ mov_w r1, __init_begin
+ mov_w r2, __init_data_begin
+ prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR
+
+ /* Xen data and BSS section. */
+ mov_w r1, __init_data_begin
+ mov_w r2, __bss_end
+ prepare_xen_region r0, r1, r2, r3, r4, r5
+
+#ifdef CONFIG_EARLY_PRINTK
+ /* Xen early UART section. */
+ mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS
+ mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE)
+ prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR
+#endif
+
+ b enable_mpu
+END(enable_boot_cpu_mm)
+
+/*
+ * We don't yet support secondary CPUs bring-up. Implement a dummy helper to
+ * please the common code.
+ */
+FUNC(enable_secondary_cpu_mm)
+ PRINT("- SMP not enabled yet -\r\n")
+1: wfe
+ b 1b
+END(enable_secondary_cpu_mm)
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
@@ -20,7 +20,16 @@
* uses r0 as a placeholder register. */
#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";"
-#ifndef __ASSEMBLY__
+#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */
+#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */
+#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */
+#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */
+
+#ifdef __ASSEMBLY__
+
+#define WRITE_SYSREG_ASM(v, name) mcr CP32(v, name)
+
+#else /* __ASSEMBLY__ */
/* C wrappers */
#define READ_CP32(name...) ({ \
@@ -84,7 +93,7 @@
/* MVFR2 is not defined on ARMv7 */
#define MVFR2_MAYBE_UNDEFINED
-#endif /* __ASSEMBLY__ */
+#endif /* !__ASSEMBLY__ */
#endif /* __ASM_ARM_ARM32_SYSREGS_H */
/*
@@ -1,6 +1,8 @@
#ifndef __ASM_ARM_CPREGS_H
#define __ASM_ARM_CPREGS_H
+#include <asm/mpu/cpregs.h>
+
/*
* AArch32 Co-processor registers.
*
new file mode 100644
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARM_MPU_CPREGS_H
+#define __ARM_MPU_CPREGS_H
+
+/* CP15 CR0: MPU Type Register */
+#define HMPUIR p15,4,c0,c0,4
+
+/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */
+#define HPRSELR p15,4,c6,c2,1
+#define HPRBAR p15,4,c6,c3,0
+#define HPRLAR p15,4,c6,c8,1
+
+/* Aliases of AArch64 names for use in common code */
+#ifdef CONFIG_ARM_32
+/* Alphabetically... */
+#define MPUIR_EL2 HMPUIR
+#define PRBAR_EL2 HPRBAR
+#define PRLAR_EL2 HPRLAR
+#define PRSELR_EL2 HPRSELR
+#endif /* CONFIG_ARM_32 */
+
+#endif /* __ARM_MPU_CPREGS_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */