| Message ID | 20250414151336.3852990-7-alejandro.lucero-palau@amd.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Type2 device basic support | expand |
On Mon, 14 Apr 2025 16:13:20 +0100 <alejandro.lucero-palau@amd.com> wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Use cxl code for registers discovery and mapping. > > Validate capabilities found based on those registers against expected > capabilities. > > Set media ready explicitly as there is no means for doing so without > a mailbox and without the related cxl register, not mandatory for type2. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com> > Reviewed-by: Zhi Wang <zhi@nvidia.com> > Acked-by: Edward Cree <ecree.xilinx@gmail.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/net/ethernet/sfc/efx_cxl.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 753d5b7d49b6..885b46c6bd5a 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -21,8 +21,11 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > { > struct efx_nic *efx = &probe_data->efx; > struct pci_dev *pci_dev = efx->pci_dev; > + DECLARE_BITMAP(expected, CXL_MAX_CAPS); Can do the = {} trick to avoid explicit clear below. > + DECLARE_BITMAP(found, CXL_MAX_CAPS); I'm not immediately able to find where found is initialized. > struct efx_cxl *cxl; > u16 dvsec; > + int rc; > > probe_data->cxl_pio_initialised = false; > > @@ -43,6 +46,31 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > if (!cxl) > return -ENOMEM; > > + bitmap_clear(expected, 0, CXL_MAX_CAPS); > + set_bit(CXL_DEV_CAP_HDM, expected); > + set_bit(CXL_DEV_CAP_HDM, expected); > + set_bit(CXL_DEV_CAP_RAS, expected); > + > + rc = cxl_pci_accel_setup_regs(pci_dev, &cxl->cxlds, found); > + if (rc) { > + pci_err(pci_dev, "CXL accel setup regs failed"); > + return rc; > + } > + > + /* > + * Checking mandatory caps are there as, at least, a subset of those > + * found. > + */ > + if (cxl_check_caps(pci_dev, expected, found)) > + return -ENXIO; > + > + /* > + * Set media ready explicitly as there are neither mailbox for checking > + * this state nor the CXL register involved, both no mandatory for not mandatory > + * type2. > + */ > + cxl->cxlds.media_ready = true; > + > probe_data->cxl = cxl; > > return 0;
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 753d5b7d49b6..885b46c6bd5a 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -21,8 +21,11 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; struct pci_dev *pci_dev = efx->pci_dev; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct efx_cxl *cxl; u16 dvsec; + int rc; probe_data->cxl_pio_initialised = false; @@ -43,6 +46,31 @@ int efx_cxl_init(struct efx_probe_data *probe_data) if (!cxl) return -ENOMEM; + bitmap_clear(expected, 0, CXL_MAX_CAPS); + set_bit(CXL_DEV_CAP_HDM, expected); + set_bit(CXL_DEV_CAP_HDM, expected); + set_bit(CXL_DEV_CAP_RAS, expected); + + rc = cxl_pci_accel_setup_regs(pci_dev, &cxl->cxlds, found); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + return rc; + } + + /* + * Checking mandatory caps are there as, at least, a subset of those + * found. + */ + if (cxl_check_caps(pci_dev, expected, found)) + return -ENXIO; + + /* + * Set media ready explicitly as there are neither mailbox for checking + * this state nor the CXL register involved, both no mandatory for + * type2. + */ + cxl->cxlds.media_ready = true; + probe_data->cxl = cxl; return 0;