diff mbox series

[v2,5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation

Message ID 20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH | expand

Commit Message

Prabhakar April 7, 2025, 4:51 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to
confirm the clock state.

According to the manual, enabling a clock requires setting the CPG_CLK_ON
bit and verifying the clock has started using the CPG_CLK_MON bit.
Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and
confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Geert Uytterhoeven April 15, 2025, 2:35 p.m. UTC | #1 
On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Update the clock enable/disable logic to follow the latest hardware
> manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to
> confirm the clock state.
>
> According to the manual, enabling a clock requires setting the CPG_CLK_ON
> bit and verifying the clock has started using the CPG_CLK_MON bit.
> Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and
> confirming the clock has stopped via the CPG_CLK_MON bit.
>
> Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
> validate CLK_ON for a more accurate clock status evaluation.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 39d81da096b2..c75ed6ed087b 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -579,11 +579,14 @@  static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
 	if (clock->mon_index >= 0) {
 		offset = GET_CLK_MON_OFFSET(clock->mon_index);
 		bitmask = BIT(clock->mon_bit);
-	} else {
-		offset = GET_CLK_ON_OFFSET(clock->on_index);
-		bitmask = BIT(clock->on_bit);
+
+		if (!(readl(priv->base + offset) & bitmask))
+			return 0;
 	}
 
+	offset = GET_CLK_ON_OFFSET(clock->on_index);
+	bitmask = BIT(clock->on_bit);
+
 	return readl(priv->base + offset) & bitmask;
 }