| Message ID | 20250415043311.3385835-10-primoz.fiser@norik.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Update PHYTEC i.MX93 DTS | expand |
On Tue, Apr 15, 2025 at 06:33:05AM +0200, Primoz Fiser wrote: subject should be "set SION bit for CMD/DATA to fix ERR052021 errata" > Implement fix for i.MX 93 silicon errata ERR052021: > > ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low > drive mode and nominal mode > Description: > uSDHC PADs have one integration issue. > When CMD/DATA lines direction change from output to input, uSDHC > controller begin sampling, the integration issue will make input > enable signal from uSDHC propagated to the PAD with a long delay, > thus the new input value on the pad comes to uSDHC lately. The > uSDHC sampled the old input value and the sampling result is wrong. > nit: add 2 char indention > Workaround: > Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will > propagate input to uSDHC with no delay, so correct value is sampled. the same here > > This issue will wrongly trigger the start bit when sample the USDHC > command response, cause the USDHC trigger command CRC/index/endbit > error, which will finally impact the tuning pass window, espically > will impact the standard tuning logic, and can't find a correct delay > cell to get the best timing. > > Based on commit bb89601282fc ("arm64: dts: imx93-11x11-evk: set SION for > cmd and data pad of USDHC"). > > Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> > --- > Changes in v2: > - new patch in v2 (split from #8) > > .../dts/freescale/imx93-phyboard-segin.dts | 37 ++++++++++--------- > 1 file changed, 20 insertions(+), 17 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts > index 541297052b62..525f52789f8b 100644 > --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts > +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts > @@ -75,39 +75,42 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e > >; > }; > > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > pinctrl_usdhc2_default: usdhc2grp { > fsl,pins = < > MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e > - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e > - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e > + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e > + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e > + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e > + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e > + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e > MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > >; > }; > > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > fsl,pins = < > MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e > - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e > - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e > - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e > - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e > + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e > + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e > + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e > + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e > + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > >; > }; > > + /* need to config the SION for data and cmd pad, refer to ERR052021 */ > pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > fsl,pins = < > MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e > - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e > - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e > - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e > - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e > - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e > - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e > + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e > + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e > + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e > + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e > + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > >; > }; > }; > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 541297052b62..525f52789f8b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -75,39 +75,42 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_default: usdhc2grp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; };
Implement fix for i.MX 93 silicon errata ERR052021: ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low drive mode and nominal mode Description: uSDHC PADs have one integration issue. When CMD/DATA lines direction change from output to input, uSDHC controller begin sampling, the integration issue will make input enable signal from uSDHC propagated to the PAD with a long delay, thus the new input value on the pad comes to uSDHC lately. The uSDHC sampled the old input value and the sampling result is wrong. Workaround: Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will propagate input to uSDHC with no delay, so correct value is sampled. This issue will wrongly trigger the start bit when sample the USDHC command response, cause the USDHC trigger command CRC/index/endbit error, which will finally impact the tuning pass window, espically will impact the standard tuning logic, and can't find a correct delay cell to get the best timing. Based on commit bb89601282fc ("arm64: dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC"). Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> --- Changes in v2: - new patch in v2 (split from #8) .../dts/freescale/imx93-phyboard-segin.dts | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-)