| Message ID | 20250407165202.197570-10-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH | expand |
Hi Prabhakar, On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add clock and reset entries for GBETH instances. Include core clocks for > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks > used as clock sources for the GBETH IP. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a09g057-cpg.c > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { > {0, 0}, > }; > > +static const struct clk_div_table dtable_2_100[] = { > + {0, 2}, > + {1, 10}, > + {2, 100}, > + {0, 0}, > +}; > + > +/* Mux clock tables */ > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver. IIUIC, they are actually Ethernet PHY signals. How is this supposed to work? The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Prabhakar, On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add clock and reset entries for GBETH instances. Include core clocks for > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks > used as clock sources for the GBETH IP. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/clk/renesas/r9a09g057-cpg.c | 72 +++++++++++++++++++++++++++++ > drivers/clk/renesas/rzv2h-cpg.h | 11 +++++ > 2 files changed, 83 insertions(+) > > diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c > index 3c40e36259fe..057bfa0e2a57 100644 > --- a/drivers/clk/renesas/r9a09g057-cpg.c > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { > DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), > DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), > > + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), > + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), > + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, > + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), > + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, > + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), > + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), > + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), > + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), > + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), > + > DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), > > /* Core Clocks */ > @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { > BUS_MSTOP(7, BIT(10))), > DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, > BUS_MSTOP(7, BIT(11))), > + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, > + BUS_MSTOP(8, BIT(5)), > + 0x300, 8, 1), CPG_SSEL0 I'm wondering if you really have to store and duplicate this info here. Can't you infer it from the parent's smux description? > + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, > + BUS_MSTOP(8, BIT(5)), > + 0x300, 12, 1), > + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, > + BUS_MSTOP(8, BIT(5)), > + 0x300, 8, 1), > + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, > + BUS_MSTOP(8, BIT(5)), > + 0x300, 12, 1), > + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, > + BUS_MSTOP(8, BIT(5))), > + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, > + BUS_MSTOP(8, BIT(5))), > + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, > + BUS_MSTOP(8, BIT(6)), > + 0x304, 8, 1), CPG_SSEL0 > + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, > + BUS_MSTOP(8, BIT(6)), > + 0x304, 12, 1), > + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, > + BUS_MSTOP(8, BIT(6)), > + 0x304, 8, 1), > + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, > + BUS_MSTOP(8, BIT(6)), > + 0x304, 12, 1), > + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, > + BUS_MSTOP(8, BIT(6))), > + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, > + BUS_MSTOP(8, BIT(6))), > DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, > BUS_MSTOP(9, BIT(4))), > DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, > @@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { > DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ > DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ > DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ > + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ > + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ > DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ > DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ > DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ > diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h > index c64cfead6dc1..e730179d92aa 100644 > --- a/drivers/clk/renesas/rzv2h-cpg.h > +++ b/drivers/clk/renesas/rzv2h-cpg.h > @@ -93,10 +93,13 @@ struct smuxed { > .width = (_width), \ > }) > > +#define CPG_SSEL0 (0x300) > +#define CPG_SSEL1 (0x304) > #define CPG_CDDIV0 (0x400) > #define CPG_CDDIV1 (0x404) > #define CPG_CDDIV3 (0x40C) > #define CPG_CDDIV4 (0x410) > +#define CPG_CSDIV0 (0x500) > > #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) > #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) > @@ -111,6 +114,14 @@ struct smuxed { > #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) > #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) > > +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) > +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) > + > +#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) > +#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) > +#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) > +#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) > + > #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) > #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) > #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add clock and reset entries for GBETH instances. Include core clocks for > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks > > used as clock sources for the GBETH IP. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { > > {0, 0}, > > }; > > > > +static const struct clk_div_table dtable_2_100[] = { > > + {0, 2}, > > + {1, 10}, > > + {2, 100}, > > + {0, 0}, > > +}; > > + > > +/* Mux clock tables */ > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; > > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver. > IIUIC, they are actually Ethernet PHY signals. > How is this supposed to work? > My intention was to add support for PHY drivers to provide the clocks and hook them up accordingly. Currently, for the RX clocks, we get a rate of 0 since they are external. # cat /sys/kernel/debug/clk/clk_summary | grep eth_0 gbeth_0_clk_tx_180_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet tx-180 gbeth_0_clk_tx_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet tx gbeth_0_clk_ptp_ref_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet ptp_ref gbeth_0_aclk_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet stmmaceth gbeth_0_aclk_csr_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet pclk gbeth_0_clk_rx_180_i 1 1 0 0 0 0 50000 Y 15c30000.ethernet rx-180 gbeth_0_clk_rx_i 1 1 0 0 0 0 50000 Y 15c30000.ethernet rx I haven’t written a prototype yet for the PHY driver to provide the clocks, but the plan is to get the initial pieces in place and then extend support for that. Is my understanding correct that the PHY should provide the clocks? Or would you suggest a different approach? Cheers, Prabhakar
Hi Prabhakar, On Tue, 15 Apr 2025 at 21:25, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Add clock and reset entries for GBETH instances. Include core clocks for > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks > > > used as clock sources for the GBETH IP. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > > > > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { > > > {0, 0}, > > > }; > > > > > > +static const struct clk_div_table dtable_2_100[] = { > > > + {0, 2}, > > > + {1, 10}, > > > + {2, 100}, > > > + {0, 0}, > > > +}; > > > + > > > +/* Mux clock tables */ > > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; > > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; > > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; > > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; > > > > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver. > > IIUIC, they are actually Ethernet PHY signals. > > How is this supposed to work? > > > My intention was to add support for PHY drivers to provide the clocks > and hook them up accordingly. Currently, for the RX clocks, we get a > rate of 0 since they are external. So the link would not be provided by DT? If these clocks are inputs to the clock controller, they should be listed in the clock controller's clock{,-name}s' properties... > I haven’t written a prototype yet for the PHY driver to provide the > clocks, but the plan is to get the initial pieces in place and then > extend support for that. > > Is my understanding correct that the PHY should provide the clocks? Or > would you suggest a different approach? The Static Mux Control Registers (CPG_SSEL[01]) registers treat them as clock inputs. However, Figure 6.3-1 ("Block Diagram of the Ethernet Interface") shows the TX clocks are bidirectional, so they can be used as either inputs or outputs? On RGMII[1], RXC is an input (PHY-to-MAC), while TXC is an output (MAC-to-PHY). I'm a bit lost on how this works, and how to model and handle this... [1] https://en.wikipedia.org/wiki/Media-independent_interface#Reduced_gigabit_media-independent_interface Gr{oetje,eeting}s, Geert
Hi Geert, On Wed, Apr 16, 2025 at 8:37 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, 15 Apr 2025 at 21:25, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Add clock and reset entries for GBETH instances. Include core clocks for > > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks > > > > used as clock sources for the GBETH IP. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Thanks for your patch! > > > > > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c > > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > > > > > > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { > > > > {0, 0}, > > > > }; > > > > > > > > +static const struct clk_div_table dtable_2_100[] = { > > > > + {0, 2}, > > > > + {1, 10}, > > > > + {2, 100}, > > > > + {0, 0}, > > > > +}; > > > > + > > > > +/* Mux clock tables */ > > > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; > > > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; > > > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; > > > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; > > > > > > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver. > > > IIUIC, they are actually Ethernet PHY signals. > > > How is this supposed to work? > > > > > My intention was to add support for PHY drivers to provide the clocks > > and hook them up accordingly. Currently, for the RX clocks, we get a > > rate of 0 since they are external. > > So the link would not be provided by DT? > If these clocks are inputs to the clock controller, they should be > listed in the clock controller's clock{,-name}s' properties... > > > I haven’t written a prototype yet for the PHY driver to provide the > > clocks, but the plan is to get the initial pieces in place and then > > extend support for that. > > > > Is my understanding correct that the PHY should provide the clocks? Or > > would you suggest a different approach? > > The Static Mux Control Registers (CPG_SSEL[01]) registers treat them as > clock inputs. However, Figure 6.3-1 ("Block Diagram of the Ethernet > Interface") shows the TX clocks are bidirectional, so they can be used > as either inputs or outputs? On RGMII[1], RXC is an input (PHY-to-MAC), > while TXC is an output (MAC-to-PHY). > I think the Figure 6.3-1 shows TX clocks are bidirectional because PFC_OEN.OEN0/1 can be used to configure input/output for the TXC pins.. I added the below POC and did some limited testing, (not the code in PHY driver is not complete as it still needs to check interface mode and depending on that register one/two clocks) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 76e6b658077a..08d2651eba59 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -105,6 +105,50 @@ L3_CA55: cache-controller-0 { }; }; + et0_rxclk: et0-rxclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + /* + * This value must be overridden by the board depending + * on PHY connection + */ + status = "disabled"; + }; + + et0_txclk: et0-txclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + /* + * This value must be overridden by the board depending + * on PHY connection + */ + status = "disabled"; + }; + + et1_rxclk: et1-rxclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + /* + * This value must be overridden by the board depending + * on PHY connection + */ + status = "disabled"; + }; + + et1_txclk: et1-txclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + /* + * This value must be overridden by the board depending + * on PHY connection + */ + status = "disabled"; + }; + gpu_opp_table: opp-table-1 { compatible = "operating-points-v2"; @@ -266,8 +310,12 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g057-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&et0_txclk>, <&et0_rxclk>, + <&et1_txclk>, <&et1_rxclk>; + clock-names = "audio_extal", "rtxin", "qextal", + "et0_txclk", "et0_rxclk", + "et1_txclk", "et1_rxclk"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index d0160ae4d4cd..3f9c9cf1a468 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -136,6 +136,11 @@ &audio_extal_clk { clock-frequency = <22579200>; }; +&cpg { + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&phy0 0>, <&phy0 1>, <&phy1 0>, <&phy1 1>; +}; + &cru0 { status = "disabled"; }; @@ -248,6 +253,8 @@ mdio { phy0: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + #clock-cells = <1>; + clock-output-names = "et0_rxclk", "et0_txclk"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; @@ -279,6 +286,8 @@ mdio { phy1: ethernet-phy@1 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + #clock-cells = <1>; + clock-output-names = "et1_rxclk", "et1_txclk"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 94c959577f03..5a0f0b9e62c6 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -23,6 +23,10 @@ enum clk_ids { CLK_AUDIO_EXTAL, CLK_RTXIN, CLK_QEXTAL, + CLK_ET0_RXCLK, + CLK_ET0_TXCLK, + CLK_ET1_RXCLK, + CLK_ET1_TXCLK, /* PLL Clocks */ CLK_PLLCM33, @@ -128,16 +132,20 @@ static const struct clk_div_table dtable_16_128[] = { }; /* Mux clock tables */ -static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; -static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; -static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; -static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" }; +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" }; +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" }; +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" }; static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), DEF_INPUT("rtxin", CLK_RTXIN), DEF_INPUT("qextal", CLK_QEXTAL), + DEF_INPUT("et0_rxclk", CLK_ET0_RXCLK), + DEF_INPUT("et0_txclk", CLK_ET0_TXCLK), + DEF_INPUT("et1_rxclk", CLK_ET1_RXCLK), + DEF_INPUT("et1_txclk", CLK_ET1_TXCLK), /* PLL Clocks */ DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 71fb4410c31b..79245b81a8dc 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -20,6 +20,7 @@ */ #include <linux/bitfield.h> +#include <linux/clk-provider.h> #include <linux/ethtool_netlink.h> #include <linux/kernel.h> #include <linux/module.h> @@ -362,6 +363,13 @@ /* Delay used to get the second part from the LTC */ #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC) +struct micrel_phy_clk { + struct phy_device *phydev; + struct clk_hw clk[2]; +}; + +static struct micrel_phy_clk phy_clk; + struct kszphy_hw_stat { const char *string; u8 reg; @@ -1527,7 +1535,11 @@ static int ksz9131_read_status(struct phy_device *phydev) if (ret < 0) return ret; - return genphy_read_status(phydev); + ret = genphy_read_status(phydev); + clk_set_rate(phy_clk.clk[0].clk, rgmii_clock(phydev->speed)); + clk_set_rate(phy_clk.clk[1].clk, rgmii_clock(phydev->speed)); + return ret; } static int ksz9131_config_aneg(struct phy_device *phydev) @@ -2272,6 +2284,41 @@ static int ksz8061_suspend(struct phy_device *phydev) return kszphy_suspend(phydev); } +static struct clk_hw *kszphy_of_clk_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int idx = clkspec->args[0]; + struct clk_hw **clkout_hw = data; + + if (idx >= ARRAY_SIZE(phy_clk.clk)) + return ERR_PTR(-EINVAL); + + return clkout_hw[idx]; +} + +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + if (phy_clk.phydev->speed == SPEED_1000) + return 125000000UL; + else if (phy_clk.phydev->speed == SPEED_100) + return 25000000UL; + else if (phy_clk.phydev->speed == SPEED_10) + return 2500000UL; + else + return 0; +} + +static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return clamp(rate, 2500000UL, 125000000UL); +} + +static const struct clk_ops phy_clk_ops = { + .recalc_rate = phy_clk_recalc_rate, + .round_rate = phy_clk_round_rate, +}; + static int kszphy_probe(struct phy_device *phydev) { const struct kszphy_type *type = phydev->drv->driver_data; @@ -2329,7 +2376,32 @@ static int kszphy_probe(struct phy_device *phydev) priv->rmii_ref_clk_sel_val = true; } - return 0; + phy_clk.phydev = phydev; + /* Register clk outputs */ + for (u8 i = 0; i < 2; i++) { + struct clk_init_data init; + const char *name; + int ret; + + phy_clk.clk[i].init = &init; + ret = of_property_read_string_index(phydev->mdio.dev.of_node, + "clock-output-names", + i, &name); + if (ret) { + phydev_err(phydev, "Failed to get clock name %d\n", i); + return ret; + } + init.name = name; + init.ops = &phy_clk_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + ret = devm_clk_hw_register(&phydev->mdio.dev, &phy_clk.clk[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(&phydev->mdio.dev, kszphy_of_clk_get, &phy_clk.clk); } static int lan8814_cable_test_start(struct phy_device *phydev) Below are the logs: root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0 gbeth_0_clk_rx_180_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet rx-180 gbeth_0_clk_rx_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet rx gbeth_0_clk_tx_180_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet tx-180 gbeth_0_clk_tx_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet tx gbeth_0_clk_ptp_ref_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet ptp_ref gbeth_0_aclk_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet stmmaceth gbeth_0_aclk_csr_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet pclk root@rzv2h-evk:~# root@rzv2h-evk:~# root@rzv2h-evk:~# root@rzv2h-evk:~# [ 44.853189] kauditd_printk_skb: 5 callbacks suppressed [ 44.853204] audit: type=1334 audit(1744888354.247:22): prog-id=18 op=UNLOAD [ 44.865320] audit: type=1334 audit(1744888354.247:23): prog-id=17 op=UNLOAD [ 44.872331] audit: type=1334 audit(1744888354.247:24): prog-id=16 op=UNLOAD root@rzv2h-evk:~# root@rzv2h-evk:~# ethtool -s end0 speed 100 [ 97.153939] renesas-gbeth 15c30000.ethernet end0: Link is Down [ 101.258899] renesas-gbeth 15c30000.ethernet end0: Link is Up - 100Mbps/Full - flow control rx/tx root@rzv2h-evk:~# root@rzv2h-evk:~# root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0 gbeth_0_clk_rx_180_i 1 1 0 25000000 0 0 50000 Y 15c30000.ethernet rx-180 gbeth_0_clk_rx_i 1 1 0 25000000 0 0 50000 Y 15c30000.ethernet rx gbeth_0_clk_tx_180_i 1 1 0 25000000 0 0 50000 Y 15c30000.ethernet tx-180 gbeth_0_clk_tx_i 1 1 0 25000000 0 0 50000 Y 15c30000.ethernet tx gbeth_0_clk_ptp_ref_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet ptp_ref gbeth_0_aclk_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet stmmaceth gbeth_0_aclk_csr_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet pclk root@rzv2h-evk:~# ethtool -s end0 speed 10 root@rzv2h-evk:~# [ 117.300170] renesas-gbeth 15c30000.ethernet end0: Link is Down [ 119.338798] renesas-gbeth 15c30000.ethernet end0: Link is Up - 10Mbps/Full - flow control rx/tx root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0 gbeth_0_clk_rx_180_i 1 1 0 2500000 0 0 50000 Y 15c30000.ethernet rx-180 gbeth_0_clk_rx_i 1 1 0 2500000 0 0 50000 Y 15c30000.ethernet rx gbeth_0_clk_tx_180_i 1 1 0 2500000 0 0 50000 Y 15c30000.ethernet tx-180 gbeth_0_clk_tx_i 1 1 0 2500000 0 0 50000 Y 15c30000.ethernet tx gbeth_0_clk_ptp_ref_i 1 1 0 125000000 0 0 50000 Y 15c30000.ethernet ptp_ref gbeth_0_aclk_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet stmmaceth gbeth_0_aclk_csr_i 1 1 0 200000000 0 0 50000 Y 15c30000.ethernet pclk Cheers, Prabhakar
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 3c40e36259fe..057bfa0e2a57 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLVDO, + CLK_PLLETH, CLK_PLLGPU, /* Internal Core Clocks */ @@ -49,6 +50,14 @@ enum clk_ids { CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, CLK_PLLVDO_CRU3, + CLK_PLLETH_DIV_250_FIX, + CLK_PLLETH_DIV_125_FIX, + CLK_CSDIV_PLLETH_GBE0, + CLK_CSDIV_PLLETH_GBE1, + CLK_SMUX2_GBE0_TXCLK, + CLK_SMUX2_GBE0_RXCLK, + CLK_SMUX2_GBE1_TXCLK, + CLK_SMUX2_GBE1_RXCLK, CLK_PLLGPU_GEAR, /* Module Clocks */ @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_100[] = { + {0, 2}, + {1, 10}, + {2, 100}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" }; +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" }; + static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -90,6 +112,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), + DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), /* Internal Core Clocks */ @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), /* Core Clocks */ @@ -130,6 +164,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), + DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), + DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { @@ -233,6 +271,38 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { BUS_MSTOP(7, BIT(10))), DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, BUS_MSTOP(7, BIT(11))), + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, + BUS_MSTOP(8, BIT(5)), + 0x300, 8, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, + BUS_MSTOP(8, BIT(5)), + 0x300, 12, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, + BUS_MSTOP(8, BIT(5)), + 0x300, 8, 1), + DEF_MOD_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, + BUS_MSTOP(8, BIT(5)), + 0x300, 12, 1), + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, + BUS_MSTOP(8, BIT(5))), + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, + BUS_MSTOP(8, BIT(5))), + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, + BUS_MSTOP(8, BIT(6)), + 0x304, 8, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, + BUS_MSTOP(8, BIT(6)), + 0x304, 12, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, + BUS_MSTOP(8, BIT(6)), + 0x304, 8, 1), + DEF_MOD_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, + BUS_MSTOP(8, BIT(6)), + 0x304, 12, 1), + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, + BUS_MSTOP(8, BIT(6))), + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, + BUS_MSTOP(8, BIT(6))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, @@ -304,6 +374,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index c64cfead6dc1..e730179d92aa 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -93,10 +93,13 @@ struct smuxed { .width = (_width), \ }) +#define CPG_SSEL0 (0x300) +#define CPG_SSEL1 (0x304) #define CPG_CDDIV0 (0x400) #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CPG_CSDIV0 (0x500) #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) @@ -111,6 +114,14 @@ struct smuxed { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) + +#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) +#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) +#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) +#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) + #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \