[2/2] arm: omap3: am35x: Disable hlt when using Davinci EMAC

Commit Message

Paul Walmsley July 19, 2012, 10:59 p.m. UTC

+ Ilya

Hi Mark

Maybe try something like this on top of the patch that disables the 
MPU DPLL autoidle?

I don't know what am35xx_enable_emac_int() is supposed to do.  It seems 
strange to clear the interrupt status bits when one is supposed to enable 
the interrupts.  Maybe Ilya can shed some light on it.


- Paul

---
 arch/arm/mach-omap2/am35xx-emac.c |   21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

Comments

Mark Greer July 20, 2012, 9:41 p.m. UTC | #1

On Thu, Jul 19, 2012 at 04:59:06PM -0600, Paul Walmsley wrote:
> + Ilya
> 
> Hi Mark
> 
> Maybe try something like this on top of the patch that disables the 
> MPU DPLL autoidle?
> 
> I don't know what am35xx_enable_emac_int() is supposed to do.  It seems 
> strange to clear the interrupt status bits when one is supposed to enable 
> the interrupts.  Maybe Ilya can shed some light on it.

Just an FYI for anyone following this thread.  Paul has contacted me
privately and said to not bother testing this patch.

Mark

Patch

diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 2c90ac6..231190e 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -23,23 +23,17 @@ 
 #include "control.h"
 #include "am35xx-emac.h"
 
-static void am35xx_enable_emac_int(void)
-{
-	u32 v;
-
-	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-	      AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
-	omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
-}
-
 static void am35xx_disable_emac_int(void)
 {
 	u32 v;
 
-	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+	/* XXX What about the misc interrupts? */
+	/*
+	 * XXX MDIO driver should handle its interrupts through the EMAC
+	 * driver
+	 */
+	v = (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+	     AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
 	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
 	omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
 }
@@ -51,7 +45,6 @@  static struct emac_platform_data am35xx_emac_pdata = {
 	.ctrl_ram_size		= AM35XX_EMAC_CNTRL_RAM_SIZE,
 	.hw_ram_addr		= AM35XX_EMAC_HW_RAM_ADDR,
 	.version		= EMAC_VERSION_2,
-	.interrupt_enable	= am35xx_enable_emac_int,
 	.interrupt_disable	= am35xx_disable_emac_int,
 };