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[2/5] clk: mmp: add clock definition for pxa168

Message ID 1343716792-10399-2-git-send-email-xiechao.mail@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chao Xie July 31, 2012, 6:39 a.m. UTC 
From: Chao Xie <chao.xie@marvell.com>

Initialize the clocks for pxa168

Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
---
 drivers/clk/mmp/Makefile     |    2 +
 drivers/clk/mmp/clk-pxa168.c |  268 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 270 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/mmp/clk-pxa168.c

Comments

Arnd Bergmann July 31, 2012, 11:54 a.m. UTC | #1 
On Tuesday 31 July 2012, Chao Xie wrote:
> +#define APBC_RTC       APBC_REG(0x28)
> +#define APBC_TWSI0     APBC_REG(0x2c)
> +#define APBC_KPC       APBC_REG(0x30)
> +#define APBC_UART0     APBC_REG(0x00)
> +#define APBC_UART1     APBC_REG(0x04)
> +#define APBC_GPIO      APBC_REG(0x08)
> +#define APBC_PWM0      APBC_REG(0x0c)
> +#define APBC_PWM1      APBC_REG(0x10)
> +#define APBC_PWM2      APBC_REG(0x14)
> +#define APBC_PWM3      APBC_REG(0x18)
> +#define APBC_SSP0      APBC_REG(0x81c)
> +#define APBC_SSP1      APBC_REG(0x820)
> +#define APBC_SSP2      APBC_REG(0x84c)
> +#define APBC_SSP3      APBC_REG(0x858)
> +#define APBC_SSP4      APBC_REG(0x85c)
> +#define APBC_TWSI1     APBC_REG(0x6c)
> +#define APBC_UART2     APBC_REG(0x70)
> +
> +#define APMU_SDH0      APMU_REG(0x54)
> +#define APMU_SDH1      APMU_REG(0x58)
> +#define APMU_USB       APMU_REG(0x5c)
> +#define APMU_DISP0     APMU_REG(0x4c)
> +#define APMU_CCIC0     APMU_REG(0x50)
> +#define APMU_DFC       APMU_REG(0x60)

Same comment as for patch 1: get the address from the device tree and just
define those macros to the offset, like:

#define APBC_RTC       0x28

apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");

	Arnd
Chao Xie Aug. 2, 2012, 7:24 a.m. UTC | #2 
On Tue, Jul 31, 2012 at 7:54 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 31 July 2012, Chao Xie wrote:
>> +#define APBC_RTC       APBC_REG(0x28)
>> +#define APBC_TWSI0     APBC_REG(0x2c)
>> +#define APBC_KPC       APBC_REG(0x30)
>> +#define APBC_UART0     APBC_REG(0x00)
>> +#define APBC_UART1     APBC_REG(0x04)
>> +#define APBC_GPIO      APBC_REG(0x08)
>> +#define APBC_PWM0      APBC_REG(0x0c)
>> +#define APBC_PWM1      APBC_REG(0x10)
>> +#define APBC_PWM2      APBC_REG(0x14)
>> +#define APBC_PWM3      APBC_REG(0x18)
>> +#define APBC_SSP0      APBC_REG(0x81c)
>> +#define APBC_SSP1      APBC_REG(0x820)
>> +#define APBC_SSP2      APBC_REG(0x84c)
>> +#define APBC_SSP3      APBC_REG(0x858)
>> +#define APBC_SSP4      APBC_REG(0x85c)
>> +#define APBC_TWSI1     APBC_REG(0x6c)
>> +#define APBC_UART2     APBC_REG(0x70)
>> +
>> +#define APMU_SDH0      APMU_REG(0x54)
>> +#define APMU_SDH1      APMU_REG(0x58)
>> +#define APMU_USB       APMU_REG(0x5c)
>> +#define APMU_DISP0     APMU_REG(0x4c)
>> +#define APMU_CCIC0     APMU_REG(0x50)
>> +#define APMU_DFC       APMU_REG(0x60)
>
> Same comment as for patch 1: get the address from the device tree and just
> define those macros to the offset, like:
>
> #define APBC_RTC       0x28
>
> apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
> clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");
>
>         Arnd
>
hi
I would like to keep the mmp_clk_register_apbc to receive the "reg
base" not "reg offset".
It will be aligned with other kind of clock register APIs.
To read out APBC base register from device tree can be added at the
clock-pxa168.c, and it can map the registers and pass to the
mmp_clk_register_apbc.
Now, i have talked to Haojian who is doing device tree maintainer in
pxa/mmp. This kind of support is not added.
I suggest that after device tree support in clock can be added later
after other functionality of the clock framework is fine.
Arnd Bergmann Aug. 2, 2012, 10:30 a.m. UTC | #3 
On Thursday 02 August 2012, Chao Xie wrote:
> > #define APBC_RTC       0x28
> >
> > apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
> > clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");
> >
> >         Arnd
> >
> hi
> I would like to keep the mmp_clk_register_apbc to receive the "reg
> base" not "reg offset".
> It will be aligned with other kind of clock register APIs.
> To read out APBC base register from device tree can be added at the
> clock-pxa168.c, and it can map the registers and pass to the
> mmp_clk_register_apbc.

Right, my mistake.

The above should have been something like

#define APBC_RTC       0x28
apbc_clks[rtc_clk] = mmp_clk_register_apbc(rtc_clk, clk32k, clock_base + APBC_RTC, 10, APBC_POWER_CTRL, mmp_clk_lock);
clk_register_clkdev(apbc_clks[rtc_clk], NULL, "sa1100-rtc");

instead, with clock_base pointing to the __iomem token for the clock controller.

> Now, i have talked to Haojian who is doing device tree maintainer in
> pxa/mmp. This kind of support is not added.
> I suggest that after device tree support in clock can be added later
> after other functionality of the clock framework is fine.

You can do device tree support as a second step, but in this first step, you
should already start using ioremap to get the virtual address of the
clock controller, rather than hardcoding it.

	Arnd
diff mbox

Patch

diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index a263cb7..8bbf882 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -3,3 +3,5 @@ 
 #
 
 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-pll2.o
+
+obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 0000000..7af4407
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,268 @@ 
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <mach/addr-map.h>
+
+#include "clk.h"
+
+#define APBC_RTC	APBC_REG(0x28)
+#define APBC_TWSI0	APBC_REG(0x2c)
+#define APBC_KPC	APBC_REG(0x30)
+#define APBC_UART0	APBC_REG(0x00)
+#define APBC_UART1	APBC_REG(0x04)
+#define APBC_GPIO	APBC_REG(0x08)
+#define APBC_PWM0	APBC_REG(0x0c)
+#define APBC_PWM1	APBC_REG(0x10)
+#define APBC_PWM2	APBC_REG(0x14)
+#define APBC_PWM3	APBC_REG(0x18)
+#define APBC_SSP0	APBC_REG(0x81c)
+#define APBC_SSP1	APBC_REG(0x820)
+#define APBC_SSP2	APBC_REG(0x84c)
+#define APBC_SSP3	APBC_REG(0x858)
+#define APBC_SSP4	APBC_REG(0x85c)
+#define APBC_TWSI1	APBC_REG(0x6c)
+#define APBC_UART2	APBC_REG(0x70)
+
+#define APMU_SDH0	APMU_REG(0x54)
+#define APMU_SDH1	APMU_REG(0x58)
+#define APMU_USB	APMU_REG(0x5c)
+#define APMU_DISP0	APMU_REG(0x4c)
+#define APMU_CCIC0	APMU_REG(0x50)
+#define APMU_DFC	APMU_REG(0x60)
+
+static DEFINE_SPINLOCK(mmp_clk_lock);
+
+enum pll_clk {
+	clk32,
+	pll1, pll1_2, pll1_4, pll1_8, pll1_16,
+	pll1_6, pll1_12, pll1_24, pll1_48, pll1_96,
+	pll1_13, pll1_13_1_5, pll1_2_1_5, pll1_3_16,
+	pll2,
+	vctcxo,
+	uart_pll,
+	pll_max,
+};
+
+enum apbc_clk {
+	uart0_clk, uart1_clk, uart2_clk,
+	pwm0_clk, pwm1_clk, pwm2_clk, pwm3_clk,
+	twsi0_clk, twsi1_clk,
+	ssp0_clk, ssp1_clk, ssp2_clk,
+	ssp3_clk, ssp4_clk,
+	gpio_clk, kpc_clk, rtc_clk,
+	uart0_mux_clk, uart1_mux_clk, uart2_mux_clk,
+	ssp0_mux_clk, ssp1_mux_clk, ssp2_mux_clk,
+	ssp3_mux_clk, ssp4_mux_clk,
+	apbc_max,
+};
+
+enum apmu_clk {
+	sdh0_mux_clk, sdh1_mux_clk,
+	sdh0_clk, sdh1_clk,
+	dfc_clk,
+	usb_clk, sph_clk,
+	disp0_mux_clk, disp0_clk,
+	disp0_hclk,
+	ccic0_mux_clk, ccic0_clk,
+	ccic0_phy_mux_clk, ccic0_phy_clk, ccic0_sphy_div_clk, ccic0_sphy_clk,
+	apmu_max,
+};
+
+static struct clk_factor_masks factor_masks = {
+	.num_mask = 0x1fff,
+	.den_mask = 0x1fff,
+	.num_shift = 16,
+	.den_shift = 0,
+};
+
+static struct clk_factor_tbl factor_tbl[] = {
+	{.num = 8125,	.den = 1536},	/* 14.745MHZ */
+};
+
+static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
+static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
+static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
+static const char *disp_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
+static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
+
+void __init pxa168_clk_init(void)
+{
+	struct clk *pll_clks[pll_max];
+	struct clk *apbc_clks[apbc_max];
+	struct clk *apmu_clks[apmu_max];
+	/* all root clocks */
+	MMP_CLK_REGISTER_FIXED_RATE(pll_clks, clk32, 32000);
+	MMP_CLK_REGISTER_FIXED_RATE(pll_clks, vctcxo, 26000000);
+	MMP_CLK_REGISTER_FIXED_RATE(pll_clks, pll1, 624000000);
+	pll_clks[pll2] = mmp_clk_register_pll2("pll2", "vctcxo", 0);
+	clk_register_clkdev(pll_clks[pll2], NULL, "pll2");
+
+	/* PLL1 */
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_2, pll1,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_4, pll1_2,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_8, pll1_4,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_16, pll1_8,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_6, pll1_2,
+					CLK_SET_RATE_PARENT, 1, 3);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_12, pll1_6,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_24, pll1_12,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_48, pll1_24,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_96, pll1_48,
+					CLK_SET_RATE_PARENT, 1, 2);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_13, pll1,
+					CLK_SET_RATE_PARENT, 1, 13);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_13_1_5, pll1_13,
+					CLK_SET_RATE_PARENT, 2, 3);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_2_1_5, pll1_2,
+					CLK_SET_RATE_PARENT, 2, 3);
+	MMP_CLK_REGISTER_FIXED_FACTOR(pll_clks, pll1_3_16, pll1,
+					CLK_SET_RATE_PARENT, 3, 16);
+	pll_clks[uart_pll] = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
+				MPMU_REG(0x14), &factor_masks, factor_tbl,
+				ARRAY_SIZE(factor_tbl));
+	clk_set_rate(pll_clks[uart_pll], 14745600);
+	/* PLL2 */
+
+	/* APBC devices without mux parent */
+	MMP_CLK_REGISTER_APBC(apbc_clks, twsi0_clk, pll1_13_1_5, 10,
+			APBC_TWSI0, 0, "pxa2xx-i2c.0", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, twsi1_clk, pll1_13_1_5, 10,
+			APBC_TWSI1, 0, "pxa2xx-i2c.1", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, gpio_clk, vctcxo, 10,
+			APBC_GPIO, 0, "pxa-gpio", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, kpc_clk, clk32k, 10,
+			APBC_KPC, 0, "pxa27x-keypad", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, rtc_clk, clk32k, 10,
+			APBC_RTC, APBC_POWER_CTRL, "sa1100-rtc", NULL,
+			&mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, pwm0_clk, pll1_48, 10,
+			APBC_PWM0, 0, "pxa168-pwm.0", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, pwm1_clk, pll1_48, 10,
+			APBC_PWM1, 0, "pxa168-pwm.1", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, pwm2_clk, pll1_48, 10,
+			APBC_PWM2, 0, "pxa168-pwm.2", NULL, &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, pwm3_clk, pll1_48, 10,
+			APBC_PWM3, 0, "pxa168-pwm.3", NULL, &mmp_clk_lock);
+
+	/* APBC devices with mux parent */
+	MMP_CLK_REGISTER_MUX(apbc_clks, uart0_mux_clk, uart_parent,
+			ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			APBC_UART0, 4, 3, 0, NULL, "uart_mux.0",
+			&mmp_clk_lock);
+	clk_set_parent(apbc_clks[uart0_mux_clk], pll_clks[uart_pll]);
+	MMP_CLK_REGISTER_APBC(apbc_clks, uart0_clk, uart0_mux_clk, 10,
+			APBC_UART0, 0, "pxa2xx-uart.0", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, uart1_mux_clk, uart_parent,
+			ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			APBC_UART1, 4, 3, 0, NULL, "uart_mux.1",
+			&mmp_clk_lock);
+	clk_set_parent(apbc_clks[uart1_mux_clk], pll_clks[uart_pll]);
+	MMP_CLK_REGISTER_APBC(apbc_clks, uart1_clk, uart1_mux_clk, 10,
+			APBC_UART1, 0, "pxa2xx-uart.1", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, uart2_mux_clk, uart_parent,
+			ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
+			APBC_UART2, 4, 3, 0, NULL, "uart_mux.2",
+			&mmp_clk_lock);
+	clk_set_parent(apbc_clks[uart2_mux_clk], pll_clks[uart_pll]);
+	MMP_CLK_REGISTER_APBC(apbc_clks, uart2_clk, uart2_mux_clk, 10,
+			APBC_UART2, 0, "pxa2xx-uart.2", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, ssp0_mux_clk, ssp_parent,
+			ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			APBC_SSP0, 4, 3, 0, NULL, "ssp_mux.0", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, ssp0_clk, ssp0_mux_clk, 10,
+			APBC_SSP0, 0, "pxa168-ssp.0", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, ssp1_mux_clk, ssp_parent,
+			ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			APBC_SSP1, 4, 3, 0, NULL, "ssp_mux.1", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, ssp1_clk, ssp1_mux_clk, 10,
+			APBC_SSP1, 0, "pxa168-ssp.1", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, ssp2_mux_clk, ssp_parent,
+			ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			APBC_SSP2, 4, 3, 0, NULL, "ssp_mux.2", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, ssp2_clk, ssp2_mux_clk, 10,
+			APBC_SSP2, 0, "pxa168-ssp.2", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, ssp3_mux_clk, ssp_parent,
+			ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			APBC_SSP3, 4, 3, 0, NULL, "ssp_mux.3", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, ssp3_clk, ssp3_mux_clk, 10,
+			APBC_SSP3, 0, "pxa168-ssp.3", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apbc_clks, ssp4_mux_clk, ssp_parent,
+			ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
+			APBC_SSP4, 4, 3, 0, NULL, "ssp_mux.4", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APBC(apbc_clks, ssp4_clk, ssp4_mux_clk, 10,
+			APBC_SSP4, 0, "pxa168-ssp.4", NULL, &mmp_clk_lock);
+
+	/* APMU devices */
+	/* nand */
+	MMP_CLK_REGISTER_APMU(apmu_clks, dfc_clk, pll1_4, APMU_DFC,
+			0x19b, "pxa3xx-nand.0", NULL, &mmp_clk_lock);
+	/* sdh */
+	MMP_CLK_REGISTER_MUX(apmu_clks, sdh0_mux_clk, sdh_parent,
+			ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			APMU_SDH0, 6, 1, 0, NULL, "sdh_mux.0", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, sdh0_clk, sdh_mux_clk, APMU_SDH0,
+			0x1b, "sdhci-pxa.0", NULL, &mmp_clk_lock);
+
+	MMP_CLK_REGISTER_MUX(apmu_clks, sdh1_mux_clk, sdh_parent,
+			ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
+			APMU_SDH1, 6, 1, 0, NULL, "sdh_mux.1", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, sdh1_clk, sdh1_mux_clk, APMU_SDH1,
+			0x1b, "sdhci-pxa.1", NULL, &mmp_clk_lock);
+
+	/* usb */
+	MMP_CLK_REGISTER_APMU(apmu_clks, usb_clk, usb_pll, APMU_USB,
+			0x9, NULL, "usb-clk", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, sph_clk, usb_pll, APMU_USB,
+			0x12, NULL, "sph-clk", &mmp_clk_lock);
+
+	/* display */
+	MMP_CLK_REGISTER_MUX(apmu_clks, disp0_mux_clk, disp_parent,
+			ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
+			APMU_DISP0, 6, 1, 0, NULL, "disp_mux.0",
+			&mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, disp0_clk, disp0_mux_clk, APMU_DISP0,
+			0x1b, "mmp-disp.0", "fnclk", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, disp0_hclk, disp0_mux_clk, APMU_DISP0,
+			0x24, "mmp-disp.0", "hclk", &mmp_clk_lock);
+
+	/* ccic */
+	MMP_CLK_REGISTER_MUX(apmu_clks, ccic0_mux_clk, ccic_parent,
+			ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
+			APMU_CCIC0, 6, 1, 0, NULL, "ccic_mux.0",
+			&mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, ccic0_clk, ccic0_mux_clk, APMU_CCIC0,
+			0x1b, "mmp-ccic.0", "fnclk", &mmp_clk_lock);
+	MMP_CLK_REGISTER_MUX(apmu_clks, ccic0_phy_mux_clk, ccic_phy_parent,
+			ARRAY_SIZE(ccic_phy_parent), CLK_SET_RATE_PARENT,
+			APMU_CCIC0, 7, 1, 0, NULL, "ccic_phy_mux.0",
+			&mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, ccic0_phy_clk, ccic0_phy_mux_clk,
+			APMU_CCIC0, 0x24, "mmp-ccic.0", "phyclk",
+			&mmp_clk_lock);
+	MMP_CLK_REGISTER_DIV(apmu_clks, ccic0_sphy_div_clk, ccic0_mux_clk,
+			0, APMU_CCIC0, 10, 5, 0,
+			"mmp-ccic.0", "sphyclk_div", &mmp_clk_lock);
+	MMP_CLK_REGISTER_APMU(apmu_clks, ccic0_sphy_clk, ccic0_sphy_div_clk,
+			APMU_CCIC0, 0x300, "mmp-ccic.0", "sphyclk",
+			&mmp_clk_lock);
+
+}