| Message ID | 1343932193-27192-2-git-send-email-eric@anholt.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 2012-08-02 11:29, Eric Anholt wrote: Yikes, who spelled caching wrong? Reviewed-by: Ben Widawsky <ben@bwidawsk.net> > --- > include/drm/i915_drm.h | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h > index 5c8fabe..7e9e9bd 100644 > --- a/include/drm/i915_drm.h > +++ b/include/drm/i915_drm.h > @@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea { > #define DRM_I915_GEM_WAIT 0x2c > #define DRM_I915_GEM_CONTEXT_CREATE 0x2d > #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e > +#define DRM_I915_GEM_SET_CACHEING 0x2f > +#define DRM_I915_GEM_GET_CACHEING 0x30 > +#define DRM_I915_REG_READ 0x31 > > #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + > DRM_I915_INIT, drm_i915_init_t) > #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + > DRM_I915_FLUSH) > @@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea { > #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + > DRM_I915_GEM_PIN, struct drm_i915_gem_pin) > #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + > DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) > #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + > DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) > +#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + > DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) > +#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + > DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) > #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + > DRM_I915_GEM_THROTTLE) > #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + > DRM_I915_GEM_ENTERVT) > #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + > DRM_I915_GEM_LEAVEVT) > @@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea { > #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + > DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) > #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE > + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) > #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE > + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) > +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + > DRM_I915_REG_READ, struct drm_i915_reg_read) > > /* Allow drivers to submit batchbuffers directly to hardware, > relying > * on the security mechanisms provided by hardware. > @@ -690,10 +696,31 @@ struct drm_i915_gem_busy { > /** Handle of the buffer to check for busy */ > __u32 handle; > > - /** Return busy status (1 if busy, 0 if idle) */ > + /** Return busy status (1 if busy, 0 if idle). > + * The high word is used to indicate on which rings the object > + * currently resides: > + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) > + */ > __u32 busy; > }; > > +#define I915_CACHEING_NONE 0 > +#define I915_CACHEING_CACHED 1 > + > +struct drm_i915_gem_cacheing { > + /** > + * Handle of the buffer to set/get the cacheing level of. */ > + __u32 handle; > + > + /** > + * Cacheing level to apply or return value > + * > + * bits0-15 are for generic cacheing control (i.e. the above > defined > + * values). bits16-31 are reserved for platform-specific variations > + * (e.g. l3$ caching on gen7). */ > + __u32 cacheing; > +}; > + > #define I915_TILING_NONE 0 > #define I915_TILING_X 1 > #define I915_TILING_Y 2 > @@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy { > __u32 pad; > }; > > +struct drm_i915_reg_read { > + __u64 offset; > + __u64 val; /* Return value */ > +}; > #endif /* _I915_DRM_H_ */
Ben Widawsky <ben@bwidawsk.net> writes: > On 2012-08-02 11:29, Eric Anholt wrote: > > Yikes, who spelled caching wrong? > Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Yeah, would be nice to get that fixed in the kernel before we have to cringe forever.
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 5c8fabe..7e9e9bd 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_WAIT 0x2c #define DRM_I915_GEM_CONTEXT_CREATE 0x2d #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e +#define DRM_I915_GEM_SET_CACHEING 0x2f +#define DRM_I915_GEM_GET_CACHEING 0x30 +#define DRM_I915_REG_READ 0x31 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) +#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) +#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) @@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -690,10 +696,31 @@ struct drm_i915_gem_busy { /** Handle of the buffer to check for busy */ __u32 handle; - /** Return busy status (1 if busy, 0 if idle) */ + /** Return busy status (1 if busy, 0 if idle). + * The high word is used to indicate on which rings the object + * currently resides: + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) + */ __u32 busy; }; +#define I915_CACHEING_NONE 0 +#define I915_CACHEING_CACHED 1 + +struct drm_i915_gem_cacheing { + /** + * Handle of the buffer to set/get the cacheing level of. */ + __u32 handle; + + /** + * Cacheing level to apply or return value + * + * bits0-15 are for generic cacheing control (i.e. the above defined + * values). bits16-31 are reserved for platform-specific variations + * (e.g. l3$ caching on gen7). */ + __u32 cacheing; +}; + #define I915_TILING_NONE 0 #define I915_TILING_X 1 #define I915_TILING_Y 2 @@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy { __u32 pad; }; +struct drm_i915_reg_read { + __u64 offset; + __u64 val; /* Return value */ +}; #endif /* _I915_DRM_H_ */