| Message ID | 1344289848-5278-1-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> On Mon, Aug 6, 2012 at 6:50 PM, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > include/pci_ids/i965_pci_ids.h | 33 ++++++++++++++- > src/mesa/drivers/dri/intel/intel_chipset.h | 67 ++++++++++++++++++++++++++++-- > src/mesa/drivers/dri/intel/intel_context.c | 35 +++++++++++++++- > 3 files changed, 130 insertions(+), 5 deletions(-) > > diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h > index e38f8d2..09dca5b 100644 > --- a/include/pci_ids/i965_pci_ids.h > +++ b/include/pci_ids/i965_pci_ids.h > @@ -28,6 +28,37 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) > CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) > CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) > CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) > +CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) > CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) > CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) > -CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2) > +CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) > +CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) > +CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) > +CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) > +CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) > +CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) > +CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) > +CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) > +CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) > +CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) > +CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) > +CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) > +CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) > +CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) > +CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) > +CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) > +CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) > +CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) > +CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) > +CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) > +CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) > +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) > +CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) > diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h > index c1d904e..9c00ba8 100644 > --- a/src/mesa/drivers/dri/intel/intel_chipset.h > +++ b/src/mesa/drivers/dri/intel/intel_chipset.h > @@ -89,9 +89,40 @@ > > #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ > #define PCI_CHIP_HASWELL_GT2 0x0412 > +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 > #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ > #define PCI_CHIP_HASWELL_M_GT2 0x0416 > -#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */ > +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 > +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ > +#define PCI_CHIP_HASWELL_S_GT2 0x041A > +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A > +#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ > +#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 > +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 > +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ > +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 > +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 > +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ > +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A > +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A > +#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ > +#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 > +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 > +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ > +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 > +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 > +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ > +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A > +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A > +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ > +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 > +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 > +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ > +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 > +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 > +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ > +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A > +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A > > #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ > devid == PCI_CHIP_I915_GM || \ > @@ -163,10 +194,40 @@ > IS_HASWELL(devid)) > > #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ > - devid == PCI_CHIP_HASWELL_M_GT1) > + devid == PCI_CHIP_HASWELL_M_GT1 || \ > + devid == PCI_CHIP_HASWELL_S_GT1 || \ > + devid == PCI_CHIP_HASWELL_SDV_GT1 || \ > + devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ > + devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ > + devid == PCI_CHIP_HASWELL_ULT_GT1 || \ > + devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ > + devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ > + devid == PCI_CHIP_HASWELL_CRW_GT1 || \ > + devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ > + devid == PCI_CHIP_HASWELL_CRW_S_GT1) > #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \ > devid == PCI_CHIP_HASWELL_M_GT2 || \ > - devid == PCI_CHIP_HASWELL_M_ULT_GT2) > + devid == PCI_CHIP_HASWELL_S_GT2 || \ > + devid == PCI_CHIP_HASWELL_SDV_GT2 || \ > + devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \ > + devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \ > + devid == PCI_CHIP_HASWELL_ULT_GT2 || \ > + devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \ > + devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ > + devid == PCI_CHIP_HASWELL_CRW_GT2 || \ > + devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ > + devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \ > + devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ > + devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) > > #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ > IS_HSW_GT2(devid)) > diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c > index 378859c..3b67f87c 100644 > --- a/src/mesa/drivers/dri/intel/intel_context.c > +++ b/src/mesa/drivers/dri/intel/intel_context.c > @@ -188,13 +188,46 @@ intelGetString(struct gl_context * ctx, GLenum name) > break; > case PCI_CHIP_HASWELL_GT1: > case PCI_CHIP_HASWELL_GT2: > + case PCI_CHIP_HASWELL_GT2_PLUS: > + case PCI_CHIP_HASWELL_SDV_GT1: > + case PCI_CHIP_HASWELL_SDV_GT2: > + case PCI_CHIP_HASWELL_SDV_GT2_PLUS: > + case PCI_CHIP_HASWELL_ULT_GT1: > + case PCI_CHIP_HASWELL_ULT_GT2: > + case PCI_CHIP_HASWELL_ULT_GT2_PLUS: > + case PCI_CHIP_HASWELL_CRW_GT1: > + case PCI_CHIP_HASWELL_CRW_GT2: > + case PCI_CHIP_HASWELL_CRW_GT2_PLUS: > chipset = "Intel(R) Haswell Desktop"; > break; > case PCI_CHIP_HASWELL_M_GT1: > case PCI_CHIP_HASWELL_M_GT2: > - case PCI_CHIP_HASWELL_M_ULT_GT2: > + case PCI_CHIP_HASWELL_M_GT2_PLUS: > + case PCI_CHIP_HASWELL_SDV_M_GT1: > + case PCI_CHIP_HASWELL_SDV_M_GT2: > + case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS: > + case PCI_CHIP_HASWELL_ULT_M_GT1: > + case PCI_CHIP_HASWELL_ULT_M_GT2: > + case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS: > + case PCI_CHIP_HASWELL_CRW_M_GT1: > + case PCI_CHIP_HASWELL_CRW_M_GT2: > + case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS: > chipset = "Intel(R) Haswell Mobile"; > break; > + case PCI_CHIP_HASWELL_S_GT1: > + case PCI_CHIP_HASWELL_S_GT2: > + case PCI_CHIP_HASWELL_S_GT2_PLUS: > + case PCI_CHIP_HASWELL_SDV_S_GT1: > + case PCI_CHIP_HASWELL_SDV_S_GT2: > + case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS: > + case PCI_CHIP_HASWELL_ULT_S_GT1: > + case PCI_CHIP_HASWELL_ULT_S_GT2: > + case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS: > + case PCI_CHIP_HASWELL_CRW_S_GT1: > + case PCI_CHIP_HASWELL_CRW_S_GT2: > + case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS: > + chipset = "Intel(R) Haswell Server"; > + break; > default: > chipset = "Unknown Intel Chipset"; > break; > -- > 1.7.11.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 08/06/2012 02:50 PM, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Do you have push access? If not, I can commit this for you.
2012/8/6 Kenneth Graunke <kenneth@whitecape.org>: > On 08/06/2012 02:50 PM, Paulo Zanoni wrote: >> From: Paulo Zanoni <paulo.r.zanoni@intel.com> >> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> > > Do you have push access? If not, I can commit this for you. I just discovered I have. Patch committed, thanks.
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index e38f8d2..09dca5b 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -28,6 +28,37 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) +CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) -CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2) +CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) +CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) +CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) +CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) +CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) +CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) +CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) +CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) +CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) +CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) +CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) +CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) +CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) +CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) +CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) +CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) +CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) +CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) +CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) +CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index c1d904e..9c00ba8 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -89,9 +89,40 @@ #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */ +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ +#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ +#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -163,10 +194,40 @@ IS_HASWELL(devid)) #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ - devid == PCI_CHIP_HASWELL_M_GT1) + devid == PCI_CHIP_HASWELL_M_GT1 || \ + devid == PCI_CHIP_HASWELL_S_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ + devid == PCI_CHIP_HASWELL_CRW_GT1 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ + devid == PCI_CHIP_HASWELL_CRW_S_GT1) #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \ devid == PCI_CHIP_HASWELL_M_GT2 || \ - devid == PCI_CHIP_HASWELL_M_ULT_GT2) + devid == PCI_CHIP_HASWELL_S_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ + devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \ + devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ + devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ IS_HSW_GT2(devid)) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 378859c..3b67f87c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -188,13 +188,46 @@ intelGetString(struct gl_context * ctx, GLenum name) break; case PCI_CHIP_HASWELL_GT1: case PCI_CHIP_HASWELL_GT2: + case PCI_CHIP_HASWELL_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_GT1: + case PCI_CHIP_HASWELL_SDV_GT2: + case PCI_CHIP_HASWELL_SDV_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_GT1: + case PCI_CHIP_HASWELL_ULT_GT2: + case PCI_CHIP_HASWELL_ULT_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_GT1: + case PCI_CHIP_HASWELL_CRW_GT2: + case PCI_CHIP_HASWELL_CRW_GT2_PLUS: chipset = "Intel(R) Haswell Desktop"; break; case PCI_CHIP_HASWELL_M_GT1: case PCI_CHIP_HASWELL_M_GT2: - case PCI_CHIP_HASWELL_M_ULT_GT2: + case PCI_CHIP_HASWELL_M_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_M_GT1: + case PCI_CHIP_HASWELL_SDV_M_GT2: + case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_M_GT1: + case PCI_CHIP_HASWELL_ULT_M_GT2: + case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_M_GT1: + case PCI_CHIP_HASWELL_CRW_M_GT2: + case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS: chipset = "Intel(R) Haswell Mobile"; break; + case PCI_CHIP_HASWELL_S_GT1: + case PCI_CHIP_HASWELL_S_GT2: + case PCI_CHIP_HASWELL_S_GT2_PLUS: + case PCI_CHIP_HASWELL_SDV_S_GT1: + case PCI_CHIP_HASWELL_SDV_S_GT2: + case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS: + case PCI_CHIP_HASWELL_ULT_S_GT1: + case PCI_CHIP_HASWELL_ULT_S_GT2: + case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS: + case PCI_CHIP_HASWELL_CRW_S_GT1: + case PCI_CHIP_HASWELL_CRW_S_GT2: + case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS: + chipset = "Intel(R) Haswell Server"; + break; default: chipset = "Unknown Intel Chipset"; break;