diff mbox

[v6,4/4] drm/i915: ironlake_write_eld code cleanup

Message ID 1344502338-28371-5-git-send-email-xingchao.wang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Wang Xingchao Aug. 9, 2012, 8:52 a.m. UTC 
Use _PIPE macro to get correct register definition for IBX/CPT, discard
old variable "i" way.

Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   24 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   22 +++++++++-------------
 2 files changed, 33 insertions(+), 13 deletions(-)

Comments

Daniel Vetter Aug. 14, 2012, 11:49 a.m. UTC | #1 
On Thu, Aug 09, 2012 at 04:52:18PM +0800, Wang Xingchao wrote:
> Use _PIPE macro to get correct register definition for IBX/CPT, discard
> old variable "i" way.
> 
> Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>

Ok, I've slurped in patches 1,2&4 for -next (with a bit of frobbing since
one of the #defines used in patch 4 is introduced in patch 3). I'll pick
up patch 3 as soon as the revised version is posted&reviewed.

Thanks for the patches&review.
-Daniel
Wang Xingchao Aug. 15, 2012, 3:29 a.m. UTC | #2 
> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Tuesday, August 14, 2012 7:49 PM
> To: Wang, Xingchao
> Cc: daniel@ffwll.ch; przanoni@gmail.com; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v6 4/4] drm/i915: ironlake_write_eld code cleanup
> 
> On Thu, Aug 09, 2012 at 04:52:18PM +0800, Wang Xingchao wrote:
> > Use _PIPE macro to get correct register definition for IBX/CPT,
> > discard old variable "i" way.
> >
> > Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
> 
> Ok, I've slurped in patches 1,2&4 for -next (with a bit of frobbing since one of
> the #defines used in patch 4 is introduced in patch 3). I'll pick up patch 3 as soon
> as the revised version is posted&reviewed.
> 

Thanks, Daniel. For patch 3 at version 7 , I had send it out separately. 

Thanks
--xingchao
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 08f8b65..392e887 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4239,7 +4239,15 @@ 
 #define G4X_HDMIW_HDMIEDID		0x6210C
 
 #define IBX_HDMIW_HDMIEDID_A		0xE2050
+#define IBX_HDMIW_HDMIEDID_B		0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+					IBX_HDMIW_HDMIEDID_A, \
+					IBX_HDMIW_HDMIEDID_B)
 #define IBX_AUD_CNTL_ST_A		0xE20B4
+#define IBX_AUD_CNTL_ST_B		0xE21B4
+#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+					IBX_AUD_CNTL_ST_A, \
+					IBX_AUD_CNTL_ST_B)
 #define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
 #define IBX_ELD_ADDRESS			(0x1f << 5)
 #define IBX_ELD_ACK			(1 << 4)
@@ -4248,7 +4256,15 @@ 
 #define IBX_CP_READYB			(1 << 1)
 
 #define CPT_HDMIW_HDMIEDID_A		0xE5050
+#define CPT_HDMIW_HDMIEDID_B		0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+					CPT_HDMIW_HDMIEDID_A, \
+					CPT_HDMIW_HDMIEDID_B)
 #define CPT_AUD_CNTL_ST_A		0xE50B4
+#define CPT_AUD_CNTL_ST_B		0xE51B4
+#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+					CPT_AUD_CNTL_ST_A, \
+					CPT_AUD_CNTL_ST_B)
 #define CPT_AUD_CNTRL_ST2		0xE50C0
 
 /* These are the 4 32-bit write offset registers for each stream
@@ -4258,7 +4274,15 @@ 
 #define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
 
 #define IBX_AUD_CONFIG_A			0xe2000
+#define IBX_AUD_CONFIG_B			0xe2100
+#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
+					IBX_AUD_CONFIG_A, \
+					IBX_AUD_CONFIG_B)
 #define CPT_AUD_CONFIG_A			0xe5000
+#define CPT_AUD_CONFIG_B			0xe5100
+#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
+					CPT_AUD_CONFIG_A, \
+					CPT_AUD_CONFIG_B)
 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
 #define   AUD_CONFIG_UPPER_N_SHIFT		20
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index be0950d..b06d5e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5171,28 +5171,24 @@  static void ironlake_write_eld(struct drm_connector *connector,
 	int aud_config;
 	int aud_cntl_st;
 	int aud_cntrl_st2;
+	int pipe = to_intel_crtc(crtc)->pipe;
 
 	if (HAS_PCH_IBX(connector->dev)) {
-		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
-		aud_config = IBX_AUD_CONFIG_A;
-		aud_cntl_st = IBX_AUD_CNTL_ST_A;
+		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+		aud_config = IBX_AUD_CFG(pipe);
+		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 	} else {
-		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
-		aud_config = CPT_AUD_CONFIG_A;
-		aud_cntl_st = CPT_AUD_CNTL_ST_A;
+		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+		aud_config = CPT_AUD_CFG(pipe);
+		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 	}
 
-	i = to_intel_crtc(crtc)->pipe;
-	hdmiw_hdmiedid += i * 0x100;
-	aud_cntl_st += i * 0x100;
-	aud_config += i * 0x100;
-
-	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
+	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 
 	i = I915_READ(aud_cntl_st);
-	i = (i >> 29) & 0x3;		/* DIP_Port_Select, 0x1 = PortB */
+	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
 	if (!i) {
 		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 		/* operate blindly on all ports */