diff mbox

ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412

Message ID 1422318.SfZfh0XoVo@amdc1227 (mailing list archive)
State New, archived
Headers show

Commit Message

Tomasz Figa Aug. 28, 2012, 11:13 a.m. UTC 
Exynos4412 uses different information register for each core. This patch
adjusts the bring-up code to take that into account.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/platsmp.c | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

Comments

Stephen Boyd Aug. 28, 2012, 4:21 p.m. UTC | #1 
On 8/28/2012 4:13 AM, Tomasz Figa wrote:
> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 36c3984..1114ced 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -34,8 +34,19 @@
>  
>  extern void exynos4_secondary_startup(void);
>  
> -#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
> -				S5P_INFORM5 : S5P_VA_SYSRAM)
> +static inline volatile void *cpu_boot_reg_base(void)

__iomem?

> +{
> +	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> +		return S5P_INFORM5;
> +	return S5P_VA_SYSRAM;
> +}
> +
> +static inline volatile void *cpu_boot_reg(int cpu)

__iomem? And why volatile?

> +{
> +	if (soc_is_exynos4412())
> +		return cpu_boot_reg_base() + 4*cpu;
> +	return cpu_boot_reg_base();
> +}
>  
>  /*
>   * control for which core is the next to come out of the secondary
> @@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
>  	 * until it receives a soft interrupt, and then the
>  	 * secondary CPU branches to this address.
>  	 */
> -	__raw_writel(virt_to_phys(exynos4_secondary_startup),
> -			CPU1_BOOT_REG);
> +	for (i = 1; i < max_cpus; ++i) {
> +		__raw_writel(virt_to_phys(exynos4_secondary_startup),
> +							cpu_boot_reg(i));

Do you need to use cpu_logical_map()?
Tomasz Figa Aug. 28, 2012, 5:43 p.m. UTC | #2 
Hi,

Thanks for reviewing the patch.

On Tuesday 28 of August 2012 09:21:40 Stephen Boyd wrote:
> On 8/28/2012 4:13 AM, Tomasz Figa wrote:
> > diff --git a/arch/arm/mach-exynos/platsmp.c
> > b/arch/arm/mach-exynos/platsmp.c index 36c3984..1114ced 100644
> > --- a/arch/arm/mach-exynos/platsmp.c
> > +++ b/arch/arm/mach-exynos/platsmp.c
> > @@ -34,8 +34,19 @@
> > 
> >  extern void exynos4_secondary_startup(void);
> > 
> > -#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
> > -				S5P_INFORM5 : S5P_VA_SYSRAM)
> > +static inline volatile void *cpu_boot_reg_base(void)
> 
> __iomem?

Sorry, bad habit. I will fix it. 
 
> > +{
> > +	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
> > +		return S5P_INFORM5;
> > +	return S5P_VA_SYSRAM;
> > +}
> > +
> > +static inline volatile void *cpu_boot_reg(int cpu)
> 
> __iomem? And why volatile?

Ditto.

> > +{
> > +	if (soc_is_exynos4412())
> > +		return cpu_boot_reg_base() + 4*cpu;
> > +	return cpu_boot_reg_base();
> > +}
> > 
> >  /*
> >  
> >   * control for which core is the next to come out of the secondary
> > 
> > @@ -195,6 +208,8 @@ void __init platform_smp_prepare_cpus(unsigned int
> > max_cpus)> 
> >  	 * until it receives a soft interrupt, and then the
> >  	 * secondary CPU branches to this address.
> >  	 */
> > 
> > -	__raw_writel(virt_to_phys(exynos4_secondary_startup),
> > -			CPU1_BOOT_REG);
> > +	for (i = 1; i < max_cpus; ++i) {
> > +		__raw_writel(virt_to_phys(exynos4_secondary_startup),
> > +							cpu_boot_reg(i));
> 
> Do you need to use cpu_logical_map()?

Correct me if I am wrong, but physical to logical CPU mapping will not be 
1:1 only if booted on physical CPU other than 0. I have not seen yet an 
Exynos-based board which does it.

However it might be wiser to use cpu_logical_map() just to be safe indeed. 
I will add it in next version of the patch.

--
Best regards,
Tomasz Figa
diff mbox

Patch

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984..1114ced 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -34,8 +34,19 @@ 
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline volatile void *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline volatile void *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*
  * control for which core is the next to come out of the secondary
@@ -138,7 +149,7 @@  int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+							cpu_boot_reg(cpu));
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)
@@ -186,6 +197,8 @@  void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int i;
+
 	if (!soc_is_exynos5250())
 		scu_enable(scu_base_addr());
 
@@ -195,6 +208,8 @@  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i) {
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+							cpu_boot_reg(i));
+	}
 }