diff mbox

[10/11] ARM: vexpress: Add config bus components and clocks to DTs

Message ID 1346689531-7212-11-git-send-email-pawel.moll@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Pawel Moll Sept. 3, 2012, 4:25 p.m. UTC 
Add description of all functions provided by Versatile Express
motherboard and daughterboards configuration controllers and
clock dependencies between devices.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
---
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi     |  136 ++++++++++++++++++++-
 arch/arm/boot/dts/vexpress-v2m.dtsi         |  136 ++++++++++++++++++++-
 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts |  103 ++++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts  |  169 +++++++++++++++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts     |   71 +++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts      |  121 +++++++++++++++++++
 6 files changed, 732 insertions(+), 4 deletions(-)

Comments

Rob Herring Sept. 4, 2012, 12:58 p.m. UTC | #1 
On 09/03/2012 11:25 AM, Pawel Moll wrote:
> Add description of all functions provided by Versatile Express
> motherboard and daughterboards configuration controllers and
> clock dependencies between devices.
> 
> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> ---
>  arch/arm/boot/dts/vexpress-v2m-rs1.dtsi     |  136 ++++++++++++++++++++-
>  arch/arm/boot/dts/vexpress-v2m.dtsi         |  136 ++++++++++++++++++++-
>  arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts |  103 ++++++++++++++++
>  arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts  |  169 +++++++++++++++++++++++++++
>  arch/arm/boot/dts/vexpress-v2p-ca5s.dts     |   71 +++++++++++
>  arch/arm/boot/dts/vexpress-v2p-ca9.dts      |  121 +++++++++++++++++++
>  6 files changed, 732 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> index d8a827b..9cc2a56 100644
> --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
> @@ -72,14 +72,20 @@
>  			#size-cells = <1>;
>  			ranges = <0 3 0 0x200000>;
>  
> -			sysreg@010000 {
> +			v2m_sysreg: sysreg@010000 {
>  				compatible = "arm,vexpress-sysreg";
>  				reg = <0x010000 0x1000>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
>  			};
>  
> -			sysctl@020000 {
> +			v2m_sysctl: sysctl@020000 {
>  				compatible = "arm,sp810", "arm,primecell";
>  				reg = <0x020000 0x1000>;
> +				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
> +				clock-names = "refclk", "timclk", "apb_pclk";

See Documentation/devicetree/bindings/arm/primecell.txt

apb_pclk should be first in the list.

Rob
Pawel Moll Sept. 4, 2012, 1:05 p.m. UTC | #2 
On Tue, 2012-09-04 at 13:58 +0100, Rob Herring wrote:
> > -			sysctl@020000 {
> > +			v2m_sysctl: sysctl@020000 {
> >  				compatible = "arm,sp810", "arm,primecell";
> >  				reg = <0x020000 0x1000>;
> > +				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
> > +				clock-names = "refclk", "timclk", "apb_pclk";
> 
> See Documentation/devicetree/bindings/arm/primecell.txt
> 
> apb_pclk should be first in the list.

Hm. Why, if you don't mind me asking? The amba_get_enable_pclk()
explicitly asks for "apb_pclk" id:

struct clk *pclk = clk_get(&pcdev->dev, "apb_pclk");

Now, let's have a look at MMCI:

                        mmci@050000 {
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x050000 0x1000>;
                                interrupts = <9 10>;
+                               cd-gpios = <&v2m_sysreg 0 0>;
+                               wp-gpios = <&v2m_sysreg 1 0>;
+                               max-frequency = <12000000>;
+                               vmmc-supply = <&v2m_fixed_3v3>;
+                               clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+                               clock-names = "mclk", "apb_pclk";
                        };

and mmci_probe() does:

        host->clk = clk_get(&dev->dev, NULL);
        if (IS_ERR(host->clk)) {
                ret = PTR_ERR(host->clk);
                host->clk = NULL;
                goto host_free;
        }       

Now, if I put "apb_pclk" first, before "mclk", the driver will get the
wrong clock.

Pawe?
Rob Herring Sept. 4, 2012, 2:31 p.m. UTC | #3 
On 09/04/2012 08:05 AM, Pawel Moll wrote:
> On Tue, 2012-09-04 at 13:58 +0100, Rob Herring wrote:
>>> -			sysctl@020000 {
>>> +			v2m_sysctl: sysctl@020000 {
>>>  				compatible = "arm,sp810", "arm,primecell";
>>>  				reg = <0x020000 0x1000>;
>>> +				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
>>> +				clock-names = "refclk", "timclk", "apb_pclk";
>>
>> See Documentation/devicetree/bindings/arm/primecell.txt
>>
>> apb_pclk should be first in the list.
> 
> Hm. Why, if you don't mind me asking? The amba_get_enable_pclk()
> explicitly asks for "apb_pclk" id:

So apb_pclk is always in the same position in the list and I had to
define something. Clock names are supposed to be optional, so we have to
be able to identify which clock is the bus clock without the name.

> struct clk *pclk = clk_get(&pcdev->dev, "apb_pclk");
> 
> Now, let's have a look at MMCI:
> 
>                         mmci@050000 {
>                                 compatible = "arm,pl180", "arm,primecell";
>                                 reg = <0x050000 0x1000>;
>                                 interrupts = <9 10>;
> +                               cd-gpios = <&v2m_sysreg 0 0>;
> +                               wp-gpios = <&v2m_sysreg 1 0>;
> +                               max-frequency = <12000000>;
> +                               vmmc-supply = <&v2m_fixed_3v3>;
> +                               clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
> +                               clock-names = "mclk", "apb_pclk";
>                         };
> 
> and mmci_probe() does:
> 
>         host->clk = clk_get(&dev->dev, NULL);
>         if (IS_ERR(host->clk)) {
>                 ret = PTR_ERR(host->clk);
>                 host->clk = NULL;
>                 goto host_free;
>         }       
> 
> Now, if I put "apb_pclk" first, before "mclk", the driver will get the
> wrong clock.

You're getting lucky with how clk_get is implemented. The driver should
be more specific with which clock it wants if there is more than 1.
Perhaps we need a clk_get_by_index() function?

Rob

> 
> Pawe?
> 
>
Pawel Moll Sept. 4, 2012, 3:37 p.m. UTC | #4 
On Tue, 2012-09-04 at 15:31 +0100, Rob Herring wrote:
> On 09/04/2012 08:05 AM, Pawel Moll wrote:
> > On Tue, 2012-09-04 at 13:58 +0100, Rob Herring wrote:
> >>> -			sysctl@020000 {
> >>> +			v2m_sysctl: sysctl@020000 {
> >>>  				compatible = "arm,sp810", "arm,primecell";
> >>>  				reg = <0x020000 0x1000>;
> >>> +				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
> >>> +				clock-names = "refclk", "timclk", "apb_pclk";
> >>
> >> See Documentation/devicetree/bindings/arm/primecell.txt
> >>
> >> apb_pclk should be first in the list.
> > 
> > Hm. Why, if you don't mind me asking? The amba_get_enable_pclk()
> > explicitly asks for "apb_pclk" id:
> 
> So apb_pclk is always in the same position in the list and I had to
> define something. Clock names are supposed to be optional, so we have to
> be able to identify which clock is the bus clock without the name.
[snip]
> You're getting lucky with how clk_get is implemented. The driver should
> be more specific with which clock it wants if there is more than 1.
> Perhaps we need a clk_get_by_index() function?

But the clocking framework doesn't know what "index", while it knows
exactly what is "id" (string). How about making the clock names
obligatory in the tree when there a node has more than one clock input?
This sounds much simpler to me and seems to be in line with the clocking
API. And the apb_pclk wouldn't have to be first/last/whatever.

Pawe?
Rob Herring Sept. 4, 2012, 5:51 p.m. UTC | #5 
On 09/04/2012 10:37 AM, Pawel Moll wrote:
> On Tue, 2012-09-04 at 15:31 +0100, Rob Herring wrote:
>> On 09/04/2012 08:05 AM, Pawel Moll wrote:
>>> On Tue, 2012-09-04 at 13:58 +0100, Rob Herring wrote:
>>>>> -			sysctl@020000 {
>>>>> +			v2m_sysctl: sysctl@020000 {
>>>>>  				compatible = "arm,sp810", "arm,primecell";
>>>>>  				reg = <0x020000 0x1000>;
>>>>> +				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
>>>>> +				clock-names = "refclk", "timclk", "apb_pclk";
>>>>
>>>> See Documentation/devicetree/bindings/arm/primecell.txt
>>>>
>>>> apb_pclk should be first in the list.
>>>
>>> Hm. Why, if you don't mind me asking? The amba_get_enable_pclk()
>>> explicitly asks for "apb_pclk" id:
>>
>> So apb_pclk is always in the same position in the list and I had to
>> define something. Clock names are supposed to be optional, so we have to
>> be able to identify which clock is the bus clock without the name.
> [snip]
>> You're getting lucky with how clk_get is implemented. The driver should
>> be more specific with which clock it wants if there is more than 1.
>> Perhaps we need a clk_get_by_index() function?
> 
> But the clocking framework doesn't know what "index", while it knows
> exactly what is "id" (string). How about making the clock names
> obligatory in the tree when there a node has more than one clock input?
> This sounds much simpler to me and seems to be in line with the clocking
> API. And the apb_pclk wouldn't have to be first/last/whatever.

I did say they are *supposed* to be optional, but the amba bus code
essentially makes them required. Ideally, Linux doesn't dictate what
goes in the dtb or not, but I don't have a problem if specific users of
the clock binding require the names.

Rob
diff mbox

Patch

diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827b..9cc2a56 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -72,14 +72,20 @@ 
 			#size-cells = <1>;
 			ranges = <0 3 0 0x200000>;
 
-			sysreg@010000 {
+			v2m_sysreg: sysreg@010000 {
 				compatible = "arm,vexpress-sysreg";
 				reg = <0x010000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			sysctl@020000 {
+			v2m_sysctl: sysctl@020000 {
 				compatible = "arm,sp810", "arm,primecell";
 				reg = <0x020000 0x1000>;
+				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
+				clock-names = "refclk", "timclk", "apb_pclk";
+				#clock-cells = <1>;
+				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 			};
 
 			/* PCI-E I2C bus */
@@ -100,66 +106,92 @@ 
 				compatible = "arm,pl041", "arm,primecell";
 				reg = <0x040000 0x1000>;
 				interrupts = <11>;
+				clocks = <&v2m_osc_clk0>;
+				clock-names = "apb_pclk";
 			};
 
 			mmci@050000 {
 				compatible = "arm,pl180", "arm,primecell";
 				reg = <0x050000 0x1000>;
 				interrupts = <9 10>;
+				cd-gpios = <&v2m_sysreg 0 0>;
+				wp-gpios = <&v2m_sysreg 1 0>;
+				max-frequency = <12000000>;
+				vmmc-supply = <&v2m_fixed_3v3>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "mclk", "apb_pclk";
 			};
 
 			kmi@060000 {
 				compatible = "arm,pl050", "arm,primecell";
 				reg = <0x060000 0x1000>;
 				interrupts = <12>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "KMIREFCLK", "apb_pclk";
 			};
 
 			kmi@070000 {
 				compatible = "arm,pl050", "arm,primecell";
 				reg = <0x070000 0x1000>;
 				interrupts = <13>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "KMIREFCLK", "apb_pclk";
 			};
 
 			v2m_serial0: uart@090000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x090000 0x1000>;
 				interrupts = <5>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial1: uart@0a0000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0a0000 0x1000>;
 				interrupts = <6>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial2: uart@0b0000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0b0000 0x1000>;
 				interrupts = <7>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial3: uart@0c0000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0c0000 0x1000>;
 				interrupts = <8>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			wdt@0f0000 {
 				compatible = "arm,sp805", "arm,primecell";
 				reg = <0x0f0000 0x1000>;
 				interrupts = <0>;
+				clocks = <&v2m_refclk32khz>, <&v2m_osc_clk0>;
+				clock-names = "wdogclk", "apb_pclk";
 			};
 
 			v2m_timer01: timer@110000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x110000 0x1000>;
 				interrupts = <2>;
+				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_osc_clk0>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
 			};
 
 			v2m_timer23: timer@120000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x120000 0x1000>;
 				interrupts = <3>;
+				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_osc_clk0>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
 			};
 
 			/* DVI I2C bus */
@@ -185,6 +217,8 @@ 
 				compatible = "arm,pl031", "arm,primecell";
 				reg = <0x170000 0x1000>;
 				interrupts = <4>;
+				clocks = <&v2m_osc_clk0>;
+				clock-names = "apb_pclk";
 			};
 
 			compact-flash@1a0000 {
@@ -198,6 +232,9 @@ 
 				compatible = "arm,pl111", "arm,primecell";
 				reg = <0x1f0000 0x1000>;
 				interrupts = <14>;
+				arm,vexpress,site = <0>;
+				clocks = <&v2m_osc_clk1>, <&v2m_osc_clk0>;
+				clock-names = "clcdclk", "apb_pclk";
 			};
 		};
 
@@ -208,5 +245,100 @@ 
 			regulator-max-microvolt = <3300000>;
 			regulator-always-on;
 		};
+
+		v2m_clk_24mhz: clk_24mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "v2m:clk_24mhz";
+		};
+
+		v2m_refclk1mhz: refclk1mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000>;
+			clock-output-names = "v2m:refclk1mhz";
+		};
+
+		v2m_refclk32khz: refclk32khz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "v2m:refclk32khz";
+		};
+
+		mcc {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <0>;
+			arm,vexpress,site = <0>; /* Motherboard */
+
+			v2m_osc_clk0: osc@0 {
+				/* MCC static memory clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <0>;
+				freq-range = <25000000 60000000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk0";
+			};
+
+			v2m_osc_clk1: osc@1 {
+				/* CLCD clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <1>;
+				freq-range = <23750000 63500000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk1";
+			};
+
+			v2m_osc_clk2: osc@2 {
+				/* IO FPGA peripheral clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <2>;
+				freq-range = <24000000 24000000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk2";
+			};
+
+			volt@0 {
+				/* Logic level voltage */
+				compatible = "arm,vexpress-config,volt";
+				reg = <0>;
+				regulator-name = "VIO";
+				regulator-always-on;
+			};
+
+			temp@0 {
+				/* MCC internal operating temperature */
+				compatible = "arm,vexpress-config,temp";
+				reg = <0>;
+				label = "MCC";
+			};
+
+			reset@0 {
+				compatible = "arm,vexpress-config,reset";
+				reg = <0>;
+			};
+
+			muxfpga@0 {
+				compatible = "arm,vexpress-config,muxfpga";
+				reg = <0>;
+			};
+
+			shutdown@0 {
+				compatible = "arm,vexpress-config,shutdown";
+				reg = <0>;
+			};
+
+			reboot@0 {
+				compatible = "arm,vexpress-config,reboot";
+				reg = <0>;
+			};
+
+			dvimode@0 {
+				compatible = "arm,vexpress-config,dvimode";
+				reg = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd..03133a8 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -71,14 +71,20 @@ 
 			#size-cells = <1>;
 			ranges = <0 7 0 0x20000>;
 
-			sysreg@00000 {
+			v2m_sysreg: sysreg@00000 {
 				compatible = "arm,vexpress-sysreg";
 				reg = <0x00000 0x1000>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			sysctl@01000 {
+			v2m_sysctl: sysctl@01000 {
 				compatible = "arm,sp810", "arm,primecell";
 				reg = <0x01000 0x1000>;
+				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_osc_clk0>;
+				clock-names = "refclk", "timclk", "apb_pclk";
+				#clock-cells = <1>;
+				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 			};
 
 			/* PCI-E I2C bus */
@@ -99,66 +105,92 @@ 
 				compatible = "arm,pl041", "arm,primecell";
 				reg = <0x04000 0x1000>;
 				interrupts = <11>;
+				clocks = <&v2m_osc_clk0>;
+				clock-names = "apb_pclk";
 			};
 
 			mmci@05000 {
 				compatible = "arm,pl180", "arm,primecell";
 				reg = <0x05000 0x1000>;
 				interrupts = <9 10>;
+				cd-gpios = <&v2m_sysreg 0 0>;
+				wp-gpios = <&v2m_sysreg 1 0>;
+				max-frequency = <12000000>;
+				vmmc-supply = <&v2m_fixed_3v3>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "mclk", "apb_pclk";
 			};
 
 			kmi@06000 {
 				compatible = "arm,pl050", "arm,primecell";
 				reg = <0x06000 0x1000>;
 				interrupts = <12>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "KMIREFCLK", "apb_pclk";
 			};
 
 			kmi@07000 {
 				compatible = "arm,pl050", "arm,primecell";
 				reg = <0x07000 0x1000>;
 				interrupts = <13>;
+				clocks = <&v2m_clk_24mhz>, <&v2m_osc_clk0>;
+				clock-names = "KMIREFCLK", "apb_pclk";
 			};
 
 			v2m_serial0: uart@09000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x09000 0x1000>;
 				interrupts = <5>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial1: uart@0a000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0a000 0x1000>;
 				interrupts = <6>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial2: uart@0b000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0b000 0x1000>;
 				interrupts = <7>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			v2m_serial3: uart@0c000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0c000 0x1000>;
 				interrupts = <8>;
+				clocks = <&v2m_osc_clk2>, <&v2m_osc_clk0>;
+				clock-names = "uartclk", "apb_pclk";
 			};
 
 			wdt@0f000 {
 				compatible = "arm,sp805", "arm,primecell";
 				reg = <0x0f000 0x1000>;
 				interrupts = <0>;
+				clocks = <&v2m_refclk32khz>, <&v2m_osc_clk0>;
+				clock-names = "wdogclk", "apb_pclk";
 			};
 
 			v2m_timer01: timer@11000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x11000 0x1000>;
 				interrupts = <2>;
+				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_osc_clk0>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
 			};
 
 			v2m_timer23: timer@12000 {
 				compatible = "arm,sp804", "arm,primecell";
 				reg = <0x12000 0x1000>;
 				interrupts = <3>;
+				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_osc_clk0>;
+				clock-names = "timclken1", "timclken2", "apb_pclk";
 			};
 
 			/* DVI I2C bus */
@@ -184,6 +216,8 @@ 
 				compatible = "arm,pl031", "arm,primecell";
 				reg = <0x17000 0x1000>;
 				interrupts = <4>;
+				clocks = <&v2m_osc_clk0>;
+				clock-names = "apb_pclk";
 			};
 
 			compact-flash@1a000 {
@@ -197,6 +231,9 @@ 
 				compatible = "arm,pl111", "arm,primecell";
 				reg = <0x1f000 0x1000>;
 				interrupts = <14>;
+				arm,vexpress,site = <0>;
+				clocks = <&v2m_osc_clk1>, <&v2m_osc_clk0>;
+				clock-names = "clcdclk", "apb_pclk";
 			};
 		};
 
@@ -207,5 +244,100 @@ 
 			regulator-max-microvolt = <3300000>;
 			regulator-always-on;
 		};
+
+		v2m_clk_24mhz: clk_24mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "v2m:clk_24mhz";
+		};
+
+		v2m_refclk1mhz: refclk1mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000>;
+			clock-output-names = "v2m:refclk1mhz";
+		};
+
+		v2m_refclk32khz: refclk32khz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "v2m:refclk32khz";
+		};
+
+		mcc {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#interrupt-cells = <0>;
+			arm,vexpress,site = <0>; /* Motherboard */
+
+			v2m_osc_clk0: osc@0 {
+				/* MCC static memory clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <0>;
+				freq-range = <25000000 60000000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk0";
+			};
+
+			v2m_osc_clk1: osc@1 {
+				/* CLCD clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <1>;
+				freq-range = <23750000 63500000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk1";
+			};
+
+			v2m_osc_clk2: osc@2 {
+				/* IO FPGA peripheral clock */
+				compatible = "arm,vexpress-config,osc";
+				reg = <2>;
+				freq-range = <24000000 24000000>;
+				#clock-cells = <0>;
+				clock-output-names = "v2m:osc_clk2";
+			};
+
+			volt@0 {
+				/* Logic level voltage */
+				compatible = "arm,vexpress-config,volt";
+				reg = <0>;
+				regulator-name = "VIO";
+				regulator-always-on;
+			};
+
+			temp@0 {
+				/* MCC internal operating temperature */
+				compatible = "arm,vexpress-config,temp";
+				reg = <0>;
+				label = "MCC";
+			};
+
+			reset@0 {
+				compatible = "arm,vexpress-config,reset";
+				reg = <0>;
+			};
+
+			muxfpga@0 {
+				compatible = "arm,vexpress-config,muxfpga";
+				reg = <0>;
+			};
+
+			shutdown@0 {
+				compatible = "arm,vexpress-config,shutdown";
+				reg = <0>;
+			};
+
+			reboot@0 {
+				compatible = "arm,vexpress-config,reboot";
+				reg = <0>;
+			};
+
+			dvimode@0 {
+				compatible = "arm,vexpress-config,dvimode";
+				reg = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34c..9297dd6 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -54,6 +54,9 @@ 
 		compatible = "arm,hdlcd";
 		reg = <0 0x2b000000 0 0x1000>;
 		interrupts = <0 85 4>;
+		arm,vexpress,site = <0xff>;
+		clocks = <&oscclk5>;
+		clock-names = "pxlclk";
 	};
 
 	memory-controller@2b0a0000 {
@@ -65,6 +68,7 @@ 
 		compatible = "arm,sp805", "arm,primecell";
 		reg = <0 0x2b060000 0 0x1000>;
 		interrupts = <98>;
+		status = "disabled";
 	};
 
 	gic: interrupt-controller@2c001000 {
@@ -163,6 +167,105 @@ 
 				<0 0 41 &gic 0 41 4>,
 				<0 0 42 &gic 0 42 4>;
 	};
+
+	dcc@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#interrupt-cells = <0>;
+		arm,vexpress,site = <0xff>; /* Master site */
+
+		osc@0 {
+			/* CPU PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <0>;
+			freq-range = <50000000 60000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk0";
+		};
+
+		osc@4 {
+			/* Multiplexed AXI master clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <4>;
+			freq-range = <20000000 40000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk4";
+		};
+
+		oscclk5: osc@5 {
+			/* HDLCD PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <5>;
+			freq-range = <23750000 165000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk5";
+		};
+
+		osc@6 {
+			/* SMB clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <6>;
+			freq-range = <20000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk6";
+		};
+
+		osc@7 {
+			/* SYS PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <7>;
+			freq-range = <20000000 60000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk7";
+		};
+
+		osc@8 {
+			/* DDR2 PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <8>;
+			freq-range = <40000000 40000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk8";
+		};
+
+		volt@0 {
+			/* CPU core voltage */
+			compatible = "arm,vexpress-config,volt";
+			reg = <0>;
+			regulator-name = "Cores";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-always-on;
+		};
+
+		amp@0 {
+			/* Total current for the two cores */
+			compatible = "arm,vexpress-config,amp";
+			reg = <0>;
+			label = "Cores";
+		};
+
+		temp@0 {
+			/* DCC internal temperature */
+			compatible = "arm,vexpress-config,temp";
+			reg = <0>;
+			label = "DCC";
+		};
+
+		power@0 {
+			/* Total power */
+			compatible = "arm,vexpress-config,power";
+			reg = <0>;
+			label = "Cores";
+		};
+
+		energy@0 {
+			/* Total energy */
+			compatible = "arm,vexpress-config,energy";
+			reg = <0>;
+			label = "Cores";
+		};
+	};
 };
 
 /include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81..a451478 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -74,12 +74,17 @@ 
 		compatible = "arm,sp805", "arm,primecell";
 		reg = <0 0x2a490000 0 0x1000>;
 		interrupts = <98>;
+		clocks = <&oscclk6a>, <&oscclk6a>;
+		clock-names = "wdogclk", "apb_pclk";
 	};
 
 	hdlcd@2b000000 {
 		compatible = "arm,hdlcd";
 		reg = <0 0x2b000000 0 0x1000>;
 		interrupts = <0 85 4>;
+		arm,vexpress,site = <0xff>;
+		clocks = <&oscclk5>;
+		clock-names = "pxlclk";
 	};
 
 	memory-controller@2b0a0000 {
@@ -183,6 +188,170 @@ 
 				<0 0 41 &gic 0 41 4>,
 				<0 0 42 &gic 0 42 4>;
 	};
+
+	oscclk6a: oscclk6a {
+		/* Reference 24MHz clock */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "oscclk6a";
+	};
+
+	dcc@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#interrupt-cells = <0>;
+		arm,vexpress,site = <0xff>; /* Master site */
+
+		osc@0 {
+			/* A15 PLL 0 reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <0>;
+			freq-range = <17000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk0";
+		};
+
+		osc@1 {
+			/* A15 PLL 1 reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <1>;
+			freq-range = <17000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk1";
+		};
+
+		osc@2 {
+			/* A7 PLL 0 reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <2>;
+			freq-range = <17000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk2";
+		};
+
+		osc@3 {
+			/* A7 PLL 1 reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <3>;
+			freq-range = <17000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk3";
+		};
+
+		osc@4 {
+			/* External AXI master clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <4>;
+			freq-range = <20000000 40000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk4";
+		};
+
+		oscclk5: osc@5 {
+			/* HDLCD PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <5>;
+			freq-range = <23750000 165000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk5";
+		};
+
+		osc@6 {
+			/* Static memory controller clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <6>;
+			freq-range = <20000000 40000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk6";
+		};
+
+		osc@7 {
+			/* SYS PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <7>;
+			freq-range = <17000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk7";
+		};
+
+		osc@8 {
+			/* DDR2 PLL reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <8>;
+			freq-range = <20000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk8";
+		};
+
+		volt@0 {
+			/* A15 CPU core voltage */
+			compatible = "arm,vexpress-config,volt";
+			reg = <0>;
+			regulator-name = "A15 Vcore";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-always-on;
+		};
+
+		volt@1 {
+			/* A7 CPU core voltage */
+			compatible = "arm,vexpress-config,volt";
+			reg = <1>;
+			regulator-name = "A7 Vcore";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-always-on;
+		};
+
+		amp@0 {
+			/* Total current for the two A15 cores */
+			compatible = "arm,vexpress-config,amp";
+			reg = <0>;
+			label = "A15 Icore";
+		};
+
+		amp@1 {
+			/* Total current for the three A7 cores */
+			compatible = "arm,vexpress-config,amp";
+			reg = <1>;
+			label = "A7 Icore";
+		};
+
+		temp@0 {
+			/* DCC internal temperature */
+			compatible = "arm,vexpress-config,temp";
+			reg = <0>;
+			label = "DCC";
+		};
+
+		power@0 {
+			/* Total power for the two A15 cores */
+			compatible = "arm,vexpress-config,power";
+			reg = <0>;
+			label = "A15 Pcore";
+		};
+		power@1 {
+			/* Total power for the three A7 cores */
+			compatible = "arm,vexpress-config,power";
+			reg = <1>;
+			label = "A7 Pcore";
+		};
+
+		energy@0 {
+			/* Total energy for the two A15 cores */
+			compatible = "arm,vexpress-config,energy";
+			reg = <0>;
+			label = "A15 Jcore";
+		};
+
+		energy@2 {
+			/* Total energy for the three A7 cores */
+			compatible = "arm,vexpress-config,energy";
+			reg = <2>;
+			label = "A7 Jcore";
+		};
+	};
 };
 
 /include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0..84b9a19 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -56,6 +56,9 @@ 
 		compatible = "arm,hdlcd";
 		reg = <0x2a110000 0x1000>;
 		interrupts = <0 85 4>;
+		arm,vexpress,site = <0xff>;
+		clocks = <&oscclk3>;
+		clock-names = "pxlclk";
 	};
 
 	memory-controller@2a150000 {
@@ -162,6 +165,74 @@ 
 				<0 0 41 &gic 0 41 4>,
 				<0 0 42 &gic 0 42 4>;
 	};
+
+	dcc@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#interrupt-cells = <0>;
+		arm,vexpress,site = <0xff>; /* Master site */
+
+		osc@0 {
+			/* CPU and internal AXI reference clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <0>;
+			freq-range = <50000000 100000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk0";
+		};
+
+		osc@1 {
+			/* Multiplexed AXI master clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <1>;
+			freq-range = <5000000 50000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk1";
+		};
+
+		osc@2 {
+			/* DDR2 */
+			compatible = "arm,vexpress-config,osc";
+			reg = <2>;
+			freq-range = <80000000 120000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk2";
+		};
+
+		oscclk3: osc@3 {
+			/* HDLCD */
+			compatible = "arm,vexpress-config,osc";
+			reg = <3>;
+			freq-range = <23750000 165000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk3";
+		};
+
+		osc@4 {
+			/* Test chip gate configuration */
+			compatible = "arm,vexpress-config,osc";
+			reg = <4>;
+			freq-range = <80000000 80000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk4";
+		};
+
+		osc@5 {
+			/* SMB clock */
+			compatible = "arm,vexpress-config,osc";
+			reg = <5>;
+			freq-range = <25000000 60000000>;
+			#clock-cells = <1>;
+			clock-output-names = "oscclk5";
+		};
+
+		temp@0 {
+			/* DCC internal operating temperature */
+			compatible = "arm,vexpress-config,temp";
+			reg = <0>;
+			label = "DCC";
+		};
+	};
 };
 
 /include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736..5a421f7 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -70,11 +70,16 @@ 
 		compatible = "arm,pl111", "arm,primecell";
 		reg = <0x10020000 0x1000>;
 		interrupts = <0 44 4>;
+		arm,vexpress,site = <0xff>;
+		clocks = <&oscclk1>, <&oscclk2>;
+		clock-names = "clcdclk", "apb_pclk";
 	};
 
 	memory-controller@100e0000 {
 		compatible = "arm,pl341", "arm,primecell";
 		reg = <0x100e0000 0x1000>;
+		clocks = <&oscclk2>;
+		clock-names = "apb_pclk";
 	};
 
 	memory-controller@100e1000 {
@@ -82,6 +87,8 @@ 
 		reg = <0x100e1000 0x1000>;
 		interrupts = <0 45 4>,
 			     <0 46 4>;
+		clocks = <&oscclk2>;
+		clock-names = "apb_pclk";
 	};
 
 	timer@100e4000 {
@@ -89,12 +96,16 @@ 
 		reg = <0x100e4000 0x1000>;
 		interrupts = <0 48 4>,
 			     <0 49 4>;
+		clocks = <&oscclk2>, <&oscclk2>;
+		clock-names = "timclk", "apb_pclk";
 	};
 
 	watchdog@100e5000 {
 		compatible = "arm,sp805", "arm,primecell";
 		reg = <0x100e5000 0x1000>;
 		interrupts = <0 51 4>;
+		clocks = <&oscclk2>, <&oscclk2>;
+		clock-names = "wdogclk", "apb_pclk";
 	};
 
 	scu@1e000000 {
@@ -192,6 +203,116 @@ 
 				<0 0 41 &gic 0 41 4>,
 				<0 0 42 &gic 0 42 4>;
 	};
+
+	dcc@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#interrupt-cells = <0>;
+		arm,vexpress,site = <0xff>; /* Master site */
+
+		osc@0 {
+			/* ACLK clock to the AXI master port on the test chip */
+			compatible = "arm,vexpress-config,osc";
+			reg = <0>;
+			freq-range = <30000000 50000000>;
+			#clock-cells = <0>;
+			clock-output-names = "extsaxiclk";
+		};
+
+		oscclk1: osc@1 {
+			/* Reference clock for the CLCD */
+			compatible = "arm,vexpress-config,osc";
+			reg = <1>;
+			freq-range = <10000000 80000000>;
+			#clock-cells = <0>;
+			clock-output-names = "clcdclk";
+		};
+
+		oscclk2: osc@2 {
+			/* Reference clock for the test chip internal PLLs */
+			compatible = "arm,vexpress-config,osc";
+			reg = <2>;
+			freq-range = <33000000 100000000>;
+			#clock-cells = <0>;
+			clock-output-names = "tcrefclk";
+		};
+
+		volt@0 {
+			/* Test Chip internal logic voltage */
+			compatible = "arm,vexpress-config,volt";
+			reg = <0>;
+			regulator-name = "VD10";
+			regulator-always-on;
+		};
+
+		volt@1 {
+			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+			compatible = "arm,vexpress-config,volt";
+			reg = <1>;
+			regulator-name = "VD10_S2";
+			regulator-always-on;
+		};
+
+		volt@2 {
+			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+			compatible = "arm,vexpress-config,volt";
+			reg = <2>;
+			regulator-name = "VD10_S3";
+			regulator-always-on;
+		};
+
+		volt@3 {
+			/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
+			compatible = "arm,vexpress-config,volt";
+			reg = <3>;
+			regulator-name = "VCC1V8";
+			regulator-always-on;
+		};
+
+		volt@4 {
+			/* DDR2 SDRAM VTT termination voltage */
+			compatible = "arm,vexpress-config,volt";
+			reg = <4>;
+			regulator-name = "DDR2VTT";
+			regulator-always-on;
+		};
+
+		volt@5 {
+			/* Local board supply for miscellaneous logic external to the Test Chip */
+			compatible = "arm,vexpress-config,volt";
+			reg = <5>;
+			regulator-name = "VCC3V3";
+			regulator-always-on;
+		};
+
+		amp@0 {
+			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+			compatible = "arm,vexpress-config,amp";
+			reg = <0>;
+			label = "VD10_S2";
+		};
+
+		amp@1 {
+			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+			compatible = "arm,vexpress-config,amp";
+			reg = <1>;
+			label = "VD10_S3";
+		};
+
+		power@0 {
+			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
+			compatible = "arm,vexpress-config,power";
+			reg = <0>;
+			label = "PVD10_S2";
+		};
+
+		power@1 {
+			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
+			compatible = "arm,vexpress-config,power";
+			reg = <1>;
+			label = "PVD10_S3";
+		};
+	};
 };
 
 /include/ "vexpress-v2m.dtsi"