| Message ID | 1346873081-1305-2-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Wed, 5 Sep 2012 21:24:40 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > Only enables the interrupt and puts a irq handler into place, doesn't > do anything yet. > > Unfortunately there's no gmbus interrupt support for gen2/3 (safe for > pnv, but there the irq is marked as "Test mode"). The basics look good, but the paranoia says I'd like for the interrupt to only be enabled as required. -Chris
On Wed, Sep 5, 2012 at 11:29 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > On Wed, 5 Sep 2012 21:24:40 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: >> Only enables the interrupt and puts a irq handler into place, doesn't >> do anything yet. >> >> Unfortunately there's no gmbus interrupt support for gen2/3 (safe for >> pnv, but there the irq is marked as "Test mode"). > > The basics look good, but the paranoia says I'd like for the interrupt > to only be enabled as required. I do that ;-) The real interrupt generation is also controlled by GMBUS4 - as long as that's 0, no interrupt shows up anywhere. And frobbing GMBUS4 is much easier than adding a bunch of of spinlocks around frobbing SDE_IIR ... -Daniel
On Wed, 5 Sep 2012 23:36:46 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > On Wed, Sep 5, 2012 at 11:29 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > On Wed, 5 Sep 2012 21:24:40 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > >> Only enables the interrupt and puts a irq handler into place, doesn't > >> do anything yet. > >> > >> Unfortunately there's no gmbus interrupt support for gen2/3 (safe for > >> pnv, but there the irq is marked as "Test mode"). > > > > The basics look good, but the paranoia says I'd like for the interrupt > > to only be enabled as required. > > I do that ;-) The real interrupt generation is also controlled by > GMBUS4 - as long as that's 0, no interrupt shows up anywhere. And > frobbing GMBUS4 is much easier than adding a bunch of of spinlocks > around frobbing SDE_IIR ... Indeed, killing it at source is preferrable all round. Are you sure GMBUS4 is always initialised to zero? So this patch looks sound, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index a61b41a..8415fa6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -596,6 +596,11 @@ out: return ret; } +static void gmbus_irq_handler(struct drm_device *dev) +{ + DRM_DEBUG_DRIVER("GMBUS interrupt\n"); +} + static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; @@ -607,7 +612,7 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) SDE_AUDIO_POWER_SHIFT); if (pch_iir & SDE_GMBUS) - DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); + gmbus_irq_handler(dev); if (pch_iir & SDE_AUDIO_HDCP_MASK) DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); @@ -650,7 +655,7 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) DRM_DEBUG_DRIVER("AUX channel interrupt\n"); if (pch_iir & SDE_GMBUS_CPT) - DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); + gmbus_irq_handler(dev); if (pch_iir & SDE_AUDIO_CP_REQ_CPT) DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); @@ -1841,12 +1846,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev) hotplug_mask = (SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT | - SDE_PORTD_HOTPLUG_CPT); + SDE_PORTD_HOTPLUG_CPT | + SDE_GMBUS_CPT); } else { hotplug_mask = (SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG | + SDE_GMBUS | SDE_AUX_MASK); } @@ -1906,7 +1913,8 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) hotplug_mask = (SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT | - SDE_PORTD_HOTPLUG_CPT); + SDE_PORTD_HOTPLUG_CPT | + SDE_GMBUS_CPT); dev_priv->pch_irq_mask = ~hotplug_mask; I915_WRITE(SDEIIR, I915_READ(SDEIIR)); @@ -1959,6 +1967,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev) POSTING_READ(VLV_IER); i915_enable_pipestat(dev_priv, 0, pipestat_enable); + i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_INTERRUPT_STATUS); i915_enable_pipestat(dev_priv, 1, pipestat_enable); I915_WRITE(VLV_IIR, 0xffffffff); @@ -2454,6 +2463,7 @@ static int i965_irq_postinstall(struct drm_device *dev) dev_priv->pipestat[0] = 0; dev_priv->pipestat[1] = 0; + i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_INTERRUPT_STATUS); /* * Enable some error detection, note the instruction error mask
Only enables the interrupt and puts a irq handler into place, doesn't do anything yet. Unfortunately there's no gmbus interrupt support for gen2/3 (safe for pnv, but there the irq is marked as "Test mode"). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)