| Message ID | 1346846336-27321-2-git-send-email-peter.ujfalusi@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
* Peter Ujfalusi <peter.ujfalusi@ti.com> [120905 04:59]: > + > + ocp { > + mcbsp1: mcbsp@48074000 { > + compatible = "ti,omap2420-mcbsp"; > + reg = <0x48074000 0xff>; > + reg-names = "mpu"; > + interrupts = <59>, /* TX interrupt */ > + <60>; /* RX interrupt */ > + interrupt-names = "tx", "rx"; > + interrupt-parent = <&intc>; > + ti,hwmods = "mcbsp1"; > + }; > + > + mcbsp2: mcbsp@48076000 { > + compatible = "ti,omap2420-mcbsp"; > + reg = <0x48076000 0xff>; > + reg-names = "mpu"; > + interrupts = <62>, /* TX interrupt */ > + <63>; /* RX interrupt */ > + interrupt-names = "tx", "rx"; > + interrupt-parent = <&intc>; > + ti,hwmods = "mcbsp2"; > + }; > + }; Hmm don't you need to specify the interrupt chip and offset for the interrupts here? Regards, Tony
Hi Tony, On 09/08/2012 12:29 AM, Tony Lindgren wrote: > * Peter Ujfalusi <peter.ujfalusi@ti.com> [120905 04:59]: >> + >> + ocp { >> + mcbsp1: mcbsp@48074000 { >> + compatible = "ti,omap2420-mcbsp"; >> + reg = <0x48074000 0xff>; >> + reg-names = "mpu"; >> + interrupts = <59>, /* TX interrupt */ >> + <60>; /* RX interrupt */ >> + interrupt-names = "tx", "rx"; >> + interrupt-parent = <&intc>; >> + ti,hwmods = "mcbsp1"; >> + }; >> + >> + mcbsp2: mcbsp@48076000 { >> + compatible = "ti,omap2420-mcbsp"; >> + reg = <0x48076000 0xff>; >> + reg-names = "mpu"; >> + interrupts = <62>, /* TX interrupt */ >> + <63>; /* RX interrupt */ >> + interrupt-names = "tx", "rx"; >> + interrupt-parent = <&intc>; >> + ti,hwmods = "mcbsp2"; >> + }; >> + }; > > Hmm don't you need to specify the interrupt chip and offset for > the interrupts here? Mmm, I'm not sure to get your question, there is the link to the interrupt-parent. The interrupt number is relative to the parent interrupt domain. So even if the INTC IRQ offset start at 32 instead of 0, DT IRQ mechanism will convert that to the proper hwirq thanks to irqdomain. In that case we should always provide interrupt number relative to the interrupt controller HW number and not assuming any Linux IRQ number offset like before. And in fact the interrupt-parent is not even needed, by default if will look to the parent to get the interrupt-controller. Extract from [1] interrupt-parent: "Because the hierarchy of the nodes in the interrupt tree might not match the device tree, the interrupt-parent property is available to make the definition of an interrupt parent explicit. The value is the phandle to the interrupt parent. If this property is missing from a device, its interrupt parent is assumed to be its device tree parent." [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf Regards, Benoit
Hi Benoit, On 09/10/2012 11:07 AM, Benoit Cousson wrote: > Hi Tony, > > On 09/08/2012 12:29 AM, Tony Lindgren wrote: >> * Peter Ujfalusi <peter.ujfalusi@ti.com> [120905 04:59]: >>> + >>> + ocp { >>> + mcbsp1: mcbsp@48074000 { >>> + compatible = "ti,omap2420-mcbsp"; >>> + reg = <0x48074000 0xff>; >>> + reg-names = "mpu"; >>> + interrupts = <59>, /* TX interrupt */ >>> + <60>; /* RX interrupt */ >>> + interrupt-names = "tx", "rx"; >>> + interrupt-parent = <&intc>; >>> + ti,hwmods = "mcbsp1"; >>> + }; >>> + >>> + mcbsp2: mcbsp@48076000 { >>> + compatible = "ti,omap2420-mcbsp"; >>> + reg = <0x48076000 0xff>; >>> + reg-names = "mpu"; >>> + interrupts = <62>, /* TX interrupt */ >>> + <63>; /* RX interrupt */ >>> + interrupt-names = "tx", "rx"; >>> + interrupt-parent = <&intc>; >>> + ti,hwmods = "mcbsp2"; >>> + }; >>> + }; >> >> Hmm don't you need to specify the interrupt chip and offset for >> the interrupts here? > > Mmm, I'm not sure to get your question, there is the link to the > interrupt-parent. > > The interrupt number is relative to the parent interrupt domain. So even > if the INTC IRQ offset start at 32 instead of 0, DT IRQ mechanism will > convert that to the proper hwirq thanks to irqdomain. > In that case we should always provide interrupt number relative to the > interrupt controller HW number and not assuming any Linux IRQ number > offset like before. > > > And in fact the interrupt-parent is not even needed, by default if will > look to the parent to get the interrupt-controller. This is true, but it makes the 'code' a bit more readable if I (we) specify the interrupt-parent. > > Extract from [1] > > interrupt-parent: > "Because the hierarchy of the nodes in the interrupt tree might not > match the device tree, the interrupt-parent property is available to > make the definition of an interrupt parent explicit. > The value is the phandle to the interrupt parent. If this property is > missing from a device, its interrupt parent is assumed to be its device > tree parent." > > [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf > > Regards, > Benoit >
* Peter Ujfalusi <peter.ujfalusi@ti.com> [120910 04:05]: > Hi Benoit, > > On 09/10/2012 11:07 AM, Benoit Cousson wrote: > > Hi Tony, > > > > On 09/08/2012 12:29 AM, Tony Lindgren wrote: > >> * Peter Ujfalusi <peter.ujfalusi@ti.com> [120905 04:59]: > >>> + > >>> + ocp { > >>> + mcbsp1: mcbsp@48074000 { > >>> + compatible = "ti,omap2420-mcbsp"; > >>> + reg = <0x48074000 0xff>; > >>> + reg-names = "mpu"; > >>> + interrupts = <59>, /* TX interrupt */ > >>> + <60>; /* RX interrupt */ > >>> + interrupt-names = "tx", "rx"; > >>> + interrupt-parent = <&intc>; > >>> + ti,hwmods = "mcbsp1"; > >>> + }; > >>> + > >>> + mcbsp2: mcbsp@48076000 { > >>> + compatible = "ti,omap2420-mcbsp"; > >>> + reg = <0x48076000 0xff>; > >>> + reg-names = "mpu"; > >>> + interrupts = <62>, /* TX interrupt */ > >>> + <63>; /* RX interrupt */ > >>> + interrupt-names = "tx", "rx"; > >>> + interrupt-parent = <&intc>; > >>> + ti,hwmods = "mcbsp2"; > >>> + }; > >>> + }; > >> > >> Hmm don't you need to specify the interrupt chip and offset for > >> the interrupts here? > > > > Mmm, I'm not sure to get your question, there is the link to the > > interrupt-parent. > > > > The interrupt number is relative to the parent interrupt domain. So even > > if the INTC IRQ offset start at 32 instead of 0, DT IRQ mechanism will > > convert that to the proper hwirq thanks to irqdomain. > > In that case we should always provide interrupt number relative to the > > interrupt controller HW number and not assuming any Linux IRQ number > > offset like before. Yes never mind, I was confused. We have #interrupt-cells = <1> and the interrupt specifier is just the interrupt offset.. Regards, Tony > > And in fact the interrupt-parent is not even needed, by default if will > > look to the parent to get the interrupt-controller. > > This is true, but it makes the 'code' a bit more readable if I (we) specify > the interrupt-parent. > > > > > Extract from [1] > > > > interrupt-parent: > > "Because the hierarchy of the nodes in the interrupt tree might not > > match the device tree, the interrupt-parent property is available to > > make the definition of an interrupt parent explicit. > > The value is the phandle to the interrupt parent. If this property is > > missing from a device, its interrupt parent is assumed to be its device > > tree parent." > > > > [1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf > > > > Regards, > > Benoit > > > > > -- > Péter
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi new file mode 100644 index 0000000..6174d3d --- /dev/null +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -0,0 +1,39 @@ +/* + * Device Tree Source for OMAP2420 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2420", "ti,omap2"; + + ocp { + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2420-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "tx", "rx"; + interrupt-parent = <&intc>; + ti,hwmods = "mcbsp2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi new file mode 100644 index 0000000..59a639a --- /dev/null +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -0,0 +1,83 @@ +/* + * Device Tree Source for OMAP243x SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "omap2.dtsi" + +/ { + compatible = "ti,omap2430", "ti,omap2"; + + ocp { + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <64>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>, /* RX interrupt */ + <61>; /* RX overflow interrupt */ + interrupt-names = "common", "tx", "rx", "rx_overflow"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + }; + + mcbsp2: mcbsp@48076000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48076000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp2"; + }; + + mcbsp3: mcbsp@4808c000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808c000 0xff>; + reg-names = "mpu"; + interrupts = <17>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3"; + }; + + mcbsp4: mcbsp@4808e000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x4808e000 0xff>; + reg-names = "mpu"; + interrupts = <18>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap2430-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <19>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + interrupt-parent = <&intc>; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + }; + }; +};
The McBSP IP within OMAP2420 and 2430 is different we need to create separate dtsi files for them. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> --- arch/arm/boot/dts/omap2420.dtsi | 39 +++++++++++++++++++ arch/arm/boot/dts/omap2430.dtsi | 83 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm/boot/dts/omap2420.dtsi create mode 100644 arch/arm/boot/dts/omap2430.dtsi