| Message ID | 1350327102-4463-10-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Oct 15, 2012 at 7:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > The old rule that the AUX registers are just an offset (+4 and +10) > from output_reg is not true anymore, since output_reg in on the CPU > and some AUX regs are on the PCH. Right, dp.output_reg is now DDI_BUF_CTL(port), note that _DATA is still _AUX_CH_CTL + 4, so could keep that logic and just have switch for DP_AUX_CH_CTL. > +#define PCH_DPB_AUX_CH_CTL 0xe4110 > +#define PCH_DPC_AUX_CH_CTL 0xe4210 > +#define PCH_DPD_AUX_CH_CTL 0xe4310 > + > +#define PCH_DPB_AUX_CH_DATA 0xe4114 > +#define PCH_DPC_AUX_CH_DATA 0xe4214 > +#define PCH_DPD_AUX_CH_DATA 0xe4314 Those defines are already there AFAICS: http://cgit.freedesktop.org/~danvet/drm-intel/tree/drivers/gpu/drm/i915/i915_reg.h#n4017
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 68ce163..84d9e69c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2548,6 +2548,14 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324 +#define PCH_DPB_AUX_CH_CTL 0xe4110 +#define PCH_DPC_AUX_CH_CTL 0xe4210 +#define PCH_DPD_AUX_CH_CTL 0xe4310 + +#define PCH_DPB_AUX_CH_DATA 0xe4114 +#define PCH_DPC_AUX_CH_DATA 0xe4214 +#define PCH_DPD_AUX_CH_DATA 0xe4314 + #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 22702df..3a5fe2f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint32_t aux_clock_divider; int try, precharge; + if (IS_HASWELL(dev)) { + switch (intel_dp->port) { + case PORT_A: + ch_ctl = DPA_AUX_CH_CTL; + ch_data = DPA_AUX_CH_DATA1; + break; + case PORT_B: + ch_ctl = PCH_DPB_AUX_CH_CTL; + ch_data = PCH_DPB_AUX_CH_DATA; + break; + case PORT_C: + ch_ctl = PCH_DPC_AUX_CH_CTL; + ch_data = PCH_DPC_AUX_CH_DATA; + break; + case PORT_D: + ch_ctl = PCH_DPD_AUX_CH_CTL; + ch_data = PCH_DPD_AUX_CH_DATA; + break; + default: + BUG(); + } + } + intel_dp_check_edp(intel_dp); /* The clock divider is based off the hrawclk, * and would like to run at 2MHz. So, take the