diff mbox

[29/36] drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoder

Message ID 1351714375-15284-30-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Oct. 31, 2012, 8:12 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

... instead of PIPECONF_INTERLACE_MASK.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Daniel Vetter Nov. 1, 2012, 4:16 p.m. UTC | #1 
On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> ... instead of PIPECONF_INTERLACE_MASK.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
but everything with bit 23 set is a reserved value. Sinc we set the
correct stuff anyway, I don't think we need to change the mask here - the
same would apply to cpt. So I'll drop this one here.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 066994f..4fbb296 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>  
>  	val &= ~TRANS_INTERLACE_MASK;
> -	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> +	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> +	    PIPECONF_INTERLACED_ILK)
>  		val |= TRANS_INTERLACED;
>  	else
>  		val |= TRANS_PROGRESSIVE;
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Paulo Zanoni Nov. 1, 2012, 4:53 p.m. UTC | #2 
Hi

2012/11/1 Daniel Vetter <daniel@ffwll.ch>:
> On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> ... instead of PIPECONF_INTERLACE_MASK.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
> but everything with bit 23 set is a reserved value. Sinc we set the
> correct stuff anyway, I don't think we need to change the mask here - the
> same would apply to cpt. So I'll drop this one here.

But here we're dealing with "pipeconf_val" which the value we read in
PIPECONF, which is on the CPU, not on the PCH.

TRANS_CONF has bits 23:21 for the interlaced mode, but PIPECONF has
bits 22:21 for the interlaced mode. We're reading from PIPECONF to
write to TRANSCONF, but the mask is being applied to pipeconf, so the
mask should be 22:21.

I still think my patch is correct.

> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 066994f..4fbb296 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>>       pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
>>
>>       val &= ~TRANS_INTERLACE_MASK;
>> -     if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
>> +     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
>> +         PIPECONF_INTERLACED_ILK)
>>               val |= TRANS_INTERLACED;
>>       else
>>               val |= TRANS_PROGRESSIVE;
>> --
>> 1.7.11.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
Daniel Vetter Nov. 1, 2012, 7:59 p.m. UTC | #3 
On Thu, Nov 01, 2012 at 02:53:40PM -0200, Paulo Zanoni wrote:
> Hi
> 
> 2012/11/1 Daniel Vetter <daniel@ffwll.ch>:
> > On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote:
> >> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>
> >> ... instead of PIPECONF_INTERLACE_MASK.
> >>
> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch,
> > but everything with bit 23 set is a reserved value. Sinc we set the
> > correct stuff anyway, I don't think we need to change the mask here - the
> > same would apply to cpt. So I'll drop this one here.
> 
> But here we're dealing with "pipeconf_val" which the value we read in
> PIPECONF, which is on the CPU, not on the PCH.
> 
> TRANS_CONF has bits 23:21 for the interlaced mode, but PIPECONF has
> bits 22:21 for the interlaced mode. We're reading from PIPECONF to
> write to TRANSCONF, but the mask is being applied to pipeconf, so the
> mask should be 22:21.
> 
> I still think my patch is correct.

Ah, now I see, thanks for the correction, patch applied.

Btw, while reading Bspec I've noticed some restrictions on the interlaced
mode we're using (i.e. progressive->interlaced conversion): We seem to
need a 7x5 panel fitter (which doesn't exist on all pipes) and have a
limit of 2048 on the source width ...
-Daniel
> 
> > -Daniel
> >
> >> ---
> >>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
> >>  1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> index 066994f..4fbb296 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> >>       pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
> >>
> >>       val &= ~TRANS_INTERLACE_MASK;
> >> -     if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> >> +     if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> >> +         PIPECONF_INTERLACED_ILK)
> >>               val |= TRANS_INTERLACED;
> >>       else
> >>               val |= TRANS_PROGRESSIVE;
> >> --
> >> 1.7.11.4
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> 
> 
> -- 
> Paulo Zanoni
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 066994f..4fbb296 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1733,7 +1733,8 @@  static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
 
 	val &= ~TRANS_INTERLACE_MASK;
-	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
+	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
+	    PIPECONF_INTERLACED_ILK)
 		val |= TRANS_INTERLACED;
 	else
 		val |= TRANS_PROGRESSIVE;