| Message ID | 1355251711-2169-1-git-send-email-damien.lespiau@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Dec 11, 2012 at 4:48 PM, Damien Lespiau <damien.lespiau@gmail.com> wrote: > FDI_RX_PLL_ENABLE I noticed that we have a restriction on PLL_ENABLE: "After enabling the FDI PLL, software must wait for a warmup period before enabling the link" warmup for this is 25us. Are we covered already with this 220 or should we increase it? I'm not sure. Other than that, feel free to use Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> -- Rodrigo Vivi Blog: http://blog.vivi.eng.br
Hi 2012/12/18 Rodrigo Vivi <rodrigo.vivi@gmail.com>: > On Tue, Dec 11, 2012 at 4:48 PM, Damien Lespiau > <damien.lespiau@gmail.com> wrote: >> FDI_RX_PLL_ENABLE > I noticed that we have a restriction on PLL_ENABLE: > "After enabling the FDI PLL, software must wait for a warmup period > before enabling the link" > > warmup for this is 25us. > Are we covered already with this 220 or should we increase it? > I'm not sure. Yes. On the Haswell doc, mode set sequence for CRT: "Enable PCH FDI Receiver PLL, wait 200 µs for warmup plus 20 µs DMI latency". Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Other than that, feel free to use > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > > > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Feb 14, 2013 at 05:51:24PM -0200, Paulo Zanoni wrote: > Hi > > 2012/12/18 Rodrigo Vivi <rodrigo.vivi@gmail.com>: > > On Tue, Dec 11, 2012 at 4:48 PM, Damien Lespiau > > <damien.lespiau@gmail.com> wrote: > >> FDI_RX_PLL_ENABLE > > I noticed that we have a restriction on PLL_ENABLE: > > "After enabling the FDI PLL, software must wait for a warmup period > > before enabling the link" > > > > warmup for this is 25us. > > Are we covered already with this 220 or should we increase it? > > I'm not sure. > > Yes. On the Haswell doc, mode set sequence for CRT: "Enable PCH FDI > Receiver PLL, wait 200 µs for warmup plus 20 µs DMI latency". > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Picked up the first patch of this series. Or does that r-b also how for the DDI patch in here? The 3rd one likely doesn't apply any more, and I don't really have an opinion about that particular bikeshed. -Daniel > > > > > Other than that, feel free to use > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > > > > > > > > > > > > -- > > Rodrigo Vivi > > Blog: http://blog.vivi.eng.br > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 557843d..31fc37a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -915,7 +915,7 @@ typedef struct drm_i915_private { bool hw_contexts_disabled; uint32_t hw_context_size; - bool fdi_rx_polarity_reversed; + u32 fdi_rx_config; struct i915_suspend_saved_registers regfile; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3f75cfa..ceeac97 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3922,7 +3922,7 @@ #define FDI_10BPC (1<<16) #define FDI_6BPC (2<<16) #define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) #define FDI_DMI_LINK_REVERSE_MASK (1<<14) #define FDI_RX_PLL_ENABLE (1<<13) #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index fe20bf7..86b557e 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -800,10 +800,14 @@ void intel_crt_init(struct drm_device *dev) dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; /* - * TODO: find a proper way to discover whether we need to set the - * polarity reversal bit or not, instead of relying on the BIOS. + * TODO: find a proper way to discover whether we need to set the the + * polarity and link reversal bits or not, instead of relying on the + * BIOS. */ - if (HAS_PCH_LPT(dev)) - dev_priv->fdi_rx_polarity_reversed = - !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT); + if (HAS_PCH_LPT(dev)) { + u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | + FDI_RX_LINK_REVERSAL_OVERRIDE; + + dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; + } } diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 4bad0f7..cb2dcc6 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -178,10 +178,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); /* Enable the PCH Receiver FDI PLL */ - rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE | - ((intel_crtc->fdi_lanes - 1) << 19); - if (dev_priv->fdi_rx_polarity_reversed) - rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT; + rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | + FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19); I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); POSTING_READ(_FDI_RXA_CTL); udelay(220);