diff mbox

[1/4] ARM: shmobile: sh73a0: fix Z and ZG clock hierarchy

Message ID 1361553474-27022-2-git-send-email-g.liakhovetski@gmx.de (mailing list archive)
State Superseded
Commit 8a444474efbe808471366fb57f31ec802846a818
Headers show

Commit Message

Guennadi Liakhovetski Feb. 22, 2013, 5:17 p.m. UTC
Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
 arch/arm/mach-shmobile/clock-sh73a0.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

Comments

Simon Horman Feb. 26, 2013, 4:29 a.m. UTC | #1
On Fri, Feb 22, 2013 at 06:17:51PM +0100, Guennadi Liakhovetski wrote:
> Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.

Thanks I have applied this to the soc5 branch and thus queued it up for v3.10.
Please let me know if you would prefer me to push it as a fix for v3.9.
And in that vein, if you regard it as -stable material.

> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> ---
>  arch/arm/mach-shmobile/clock-sh73a0.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
> index 5fa106b..71843dd 100644
> --- a/arch/arm/mach-shmobile/clock-sh73a0.c
> +++ b/arch/arm/mach-shmobile/clock-sh73a0.c
> @@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
>  
>  static struct clk div4_clks[DIV4_NR] = {
>  	[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
> -	[DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
> +	[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
>  	[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
>  	[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
>  	[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
>  	[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
> -	[DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
> +	[DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
>  	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
>  	[DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
>  	[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
> -- 
> 1.7.2.5
> 
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Magnus Damm Feb. 26, 2013, 5:36 a.m. UTC | #2
On Tue, Feb 26, 2013 at 1:29 PM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Feb 22, 2013 at 06:17:51PM +0100, Guennadi Liakhovetski wrote:
>> Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
>
> Thanks I have applied this to the soc5 branch and thus queued it up for v3.10.
> Please let me know if you would prefer me to push it as a fix for v3.9.
> And in that vein, if you regard it as -stable material.

Thanks.

Perhaps other people disagree, but I recommend not being so trigger
happy with -stable unless it will potentially give us some upside.
AFAIK there is no in-tree consumer of this clock anyway, so involving
-stable without further testing seems like a lot of hassle with no
real benefit.

Cheers,

/ magnus
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Simon Horman Feb. 26, 2013, 5:43 a.m. UTC | #3
On Tue, Feb 26, 2013 at 02:36:24PM +0900, Magnus Damm wrote:
> On Tue, Feb 26, 2013 at 1:29 PM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, Feb 22, 2013 at 06:17:51PM +0100, Guennadi Liakhovetski wrote:
> >> Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
> >
> > Thanks I have applied this to the soc5 branch and thus queued it up for v3.10.
> > Please let me know if you would prefer me to push it as a fix for v3.9.
> > And in that vein, if you regard it as -stable material.
> 
> Thanks.
> 
> Perhaps other people disagree, but I recommend not being so trigger
> happy with -stable unless it will potentially give us some upside.
> AFAIK there is no in-tree consumer of this clock anyway, so involving
> -stable without further testing seems like a lot of hassle with no
> real benefit.

If there is no in-tree consumer then it is not v3.9 or -stable material.

Thanks!
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Guennadi Liakhovetski Feb. 26, 2013, 6:09 a.m. UTC | #4
Hi Simon

On Tue, 26 Feb 2013, Simon Horman wrote:

> On Tue, Feb 26, 2013 at 02:36:24PM +0900, Magnus Damm wrote:
> > On Tue, Feb 26, 2013 at 1:29 PM, Simon Horman <horms@verge.net.au> wrote:
> > > On Fri, Feb 22, 2013 at 06:17:51PM +0100, Guennadi Liakhovetski wrote:
> > >> Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
> > >
> > > Thanks I have applied this to the soc5 branch and thus queued it up for v3.10.
> > > Please let me know if you would prefer me to push it as a fix for v3.9.
> > > And in that vein, if you regard it as -stable material.
> > 
> > Thanks.
> > 
> > Perhaps other people disagree, but I recommend not being so trigger
> > happy with -stable unless it will potentially give us some upside.
> > AFAIK there is no in-tree consumer of this clock anyway, so involving
> > -stable without further testing seems like a lot of hassle with no
> > real benefit.
> 
> If there is no in-tree consumer then it is not v3.9 or -stable material.

Just to confirm, that I'm not aware of any current consumers of these 
clocks, so, no rush with stable.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Simon Horman Feb. 26, 2013, 12:15 p.m. UTC | #5
On Tue, Feb 26, 2013 at 07:09:00AM +0100, Guennadi Liakhovetski wrote:
> Hi Simon
> 
> On Tue, 26 Feb 2013, Simon Horman wrote:
> 
> > On Tue, Feb 26, 2013 at 02:36:24PM +0900, Magnus Damm wrote:
> > > On Tue, Feb 26, 2013 at 1:29 PM, Simon Horman <horms@verge.net.au> wrote:
> > > > On Fri, Feb 22, 2013 at 06:17:51PM +0100, Guennadi Liakhovetski wrote:
> > > >> Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1.
> > > >
> > > > Thanks I have applied this to the soc5 branch and thus queued it up for v3.10.
> > > > Please let me know if you would prefer me to push it as a fix for v3.9.
> > > > And in that vein, if you regard it as -stable material.
> > > 
> > > Thanks.
> > > 
> > > Perhaps other people disagree, but I recommend not being so trigger
> > > happy with -stable unless it will potentially give us some upside.
> > > AFAIK there is no in-tree consumer of this clock anyway, so involving
> > > -stable without further testing seems like a lot of hassle with no
> > > real benefit.
> > 
> > If there is no in-tree consumer then it is not v3.9 or -stable material.
> 
> Just to confirm, that I'm not aware of any current consumers of these 
> clocks, so, no rush with stable.

Thanks. I'll leave it queued up for 3.10.
--
To unsubscribe from this list: send the line "unsubscribe linux-sh" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff mbox

Patch

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 5fa106b..71843dd 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -265,12 +265,12 @@  enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-	[DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+	[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
 	[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
 	[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
 	[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
 	[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-	[DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+	[DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
 	[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
 	[DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
 	[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),