| Message ID | 1363204194-19487-6-git-send-email-ldewangan@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 03/13/2013 01:49 PM, Laxman Dewangan wrote: > NVIDIA's Tegra114 has 6 spi controllers. These controllers are > redesign on T114 with different register interface. > diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi > + reg = <0x7000d400 0x200>; ... > + reg = <0x7000d600 0x200>; ... > + reg = <0x7000d480 0x200>; ... > + reg = <0x7000da00 0x200>; ... > + reg = <0x7000dc00 0x200>; ... > + reg = <0x7000de00 0x200>; I assume that third entry should be 0x7000d800 not 0x7000d480; the TRM certainly thinks so. I fixed this up when I applied this patch. I've applied the series to Tegra's for-3.10/dt branch. I made a few node/property ordering changes for consistency, and some capitalization fixes in the commit subjects/descriptions.
On Saturday 16 March 2013 12:12 AM, Stephen Warren wrote: > On 03/13/2013 01:49 PM, Laxman Dewangan wrote: >> NVIDIA's Tegra114 has 6 spi controllers. These controllers are >> redesign on T114 with different register interface. >> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi >> + reg = <0x7000d400 0x200>; > ... >> + reg = <0x7000d600 0x200>; > ... >> + reg = <0x7000d480 0x200>; > ... >> + reg = <0x7000da00 0x200>; > ... >> + reg = <0x7000dc00 0x200>; > ... >> + reg = <0x7000de00 0x200>; > I assume that third entry should be 0x7000d800 not 0x7000d480; the TRM > certainly thinks so. I fixed this up when I applied this patch. Yes, this is bug in my patch and unfortunately exist in tegra20 and tegra30 also. grep d480 tegra* tegra114.dtsi: reg = <0x7000d480 0x200>; tegra20.dtsi: reg = <0x7000d480 0x200>; tegra30.dtsi: reg = <0x7000d480 0x200>; We need to fix this. I will post a patch now to correct it. > > I've applied the series to Tegra's for-3.10/dt branch. I made a few > node/property ordering changes for consistency, and some capitalization > fixes in the commit subjects/descriptions. Thank you very much for taking care of this.
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index d2bbfaf..95c4369 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -212,6 +212,78 @@ clock-names = "div-clk"; }; + spi@7000d400 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 41>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 44>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 46>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 68>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 104>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 105>; + clock-names = "spi"; + status = "disabled"; + }; + rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>;
NVIDIA's Tegra114 has 6 spi controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- Changes from V1: - None Changes fro V2: - Rebase to for-3.10/dt of Stephen's Tegra tree. arch/arm/boot/dts/tegra114.dtsi | 72 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-)