diff mbox

[3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

Message ID 1365457784-3412-4-git-send-email-rodrigo.vivi@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi April 8, 2013, 9:49 p.m. UTC 
Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 5 insertions(+)

Comments

Ville Syrjala April 9, 2013, 8:37 a.m. UTC | #1 
On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote:
> Display register 46500h bit 23 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.

So should we enable it again after FBC is disabled to avoid wasting
power?

> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2340bc2..2ef0292 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -863,6 +863,9 @@
>  					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \
>  					     _HSW_PIPE_SLICE_CHICKEN_1_B)
>  
> +#define HSW_CLKGATE_DISABLE_PART_1	0x46500
> +#define   HSW_DPFC_GATING_DISABLE	(1<<23)
> +
>  /*
>   * GPIO regs
>   */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0628a84..f2ce541 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -281,6 +281,8 @@ static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  	/* WaFbcAsynchFlipDisableFbcQueue */
>  	I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
>  		   HSW_BYPASS_FBC_QUEUE);
> +	/* WaFbcDisableDpfcClockGating */
> +	I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);
>  
>  	if (obj->fence_reg != I915_FENCE_REG_NONE) {
>  		I915_WRITE(SNB_DPFC_CTL_SA,
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Rodrigo Vivi April 9, 2013, 6:05 p.m. UTC | #2 
On Tue, Apr 9, 2013 at 5:37 AM, Ville Syrjälä <ville.syrjala@linux.intel.com
> wrote:

> On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote:
> > Display register 46500h bit 23 must be set to 1b for the entire time that
> > Frame Buffer Compression is enabled.
>
> So should we enable it again after FBC is disabled to avoid wasting
> power?
>

I didn't take the opposite direction because it wasn't explicit.
I tested to enabled it again after FBC is disabled but I didn't see any
difference.
So, you suggestion is to enable back anyway?


>
> >
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> >  drivers/gpu/drm/i915/intel_pm.c | 2 ++
> >  2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index 2340bc2..2ef0292 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -863,6 +863,9 @@
> >                                            _HSW_PIPE_SLICE_CHICKEN_1_A,
> + \
> >                                            _HSW_PIPE_SLICE_CHICKEN_1_B)
> >
> > +#define HSW_CLKGATE_DISABLE_PART_1   0x46500
> > +#define   HSW_DPFC_GATING_DISABLE    (1<<23)
> > +
> >  /*
> >   * GPIO regs
> >   */
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> > index 0628a84..f2ce541 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -281,6 +281,8 @@ static void haswell_enable_fbc(struct drm_crtc
> *crtc, unsigned long interval)
> >       /* WaFbcAsynchFlipDisableFbcQueue */
> >       I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> >                  HSW_BYPASS_FBC_QUEUE);
> > +     /* WaFbcDisableDpfcClockGating */
> > +     I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);
> >
> >       if (obj->fence_reg != I915_FENCE_REG_NONE) {
> >               I915_WRITE(SNB_DPFC_CTL_SA,
> > --
> > 1.8.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
>
Ville Syrjala April 10, 2013, 8:07 a.m. UTC | #3 
On Tue, Apr 09, 2013 at 03:05:10PM -0300, Rodrigo Vivi wrote:
> On Tue, Apr 9, 2013 at 5:37 AM, Ville Syrjälä <ville.syrjala@linux.intel.com
> > wrote:
> 
> > On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote:
> > > Display register 46500h bit 23 must be set to 1b for the entire time that
> > > Frame Buffer Compression is enabled.
> >
> > So should we enable it again after FBC is disabled to avoid wasting
> > power?
> >
> 
> I didn't take the opposite direction because it wasn't explicit.
> I tested to enabled it again after FBC is disabled but I didn't see any
> difference.
> So, you suggestion is to enable back anyway?

Perhaps. The idea was that it might save some tiny amount of power.

> 
> >
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > >  drivers/gpu/drm/i915/intel_pm.c | 2 ++
> > >  2 files changed, 5 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 2340bc2..2ef0292 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -863,6 +863,9 @@
> > >                                            _HSW_PIPE_SLICE_CHICKEN_1_A,
> > + \
> > >                                            _HSW_PIPE_SLICE_CHICKEN_1_B)
> > >
> > > +#define HSW_CLKGATE_DISABLE_PART_1   0x46500
> > > +#define   HSW_DPFC_GATING_DISABLE    (1<<23)
> > > +
> > >  /*
> > >   * GPIO regs
> > >   */
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 0628a84..f2ce541 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -281,6 +281,8 @@ static void haswell_enable_fbc(struct drm_crtc
> > *crtc, unsigned long interval)
> > >       /* WaFbcAsynchFlipDisableFbcQueue */
> > >       I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> > >                  HSW_BYPASS_FBC_QUEUE);
> > > +     /* WaFbcDisableDpfcClockGating */
> > > +     I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);
> > >
> > >       if (obj->fence_reg != I915_FENCE_REG_NONE) {
> > >               I915_WRITE(SNB_DPFC_CTL_SA,
> > > --
> > > 1.8.1.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> >
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2340bc2..2ef0292 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -863,6 +863,9 @@ 
 					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \
 					     _HSW_PIPE_SLICE_CHICKEN_1_B)
 
+#define HSW_CLKGATE_DISABLE_PART_1	0x46500
+#define   HSW_DPFC_GATING_DISABLE	(1<<23)
+
 /*
  * GPIO regs
  */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0628a84..f2ce541 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -281,6 +281,8 @@  static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 	/* WaFbcAsynchFlipDisableFbcQueue */
 	I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 		   HSW_BYPASS_FBC_QUEUE);
+	/* WaFbcDisableDpfcClockGating */
+	I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);
 
 	if (obj->fence_reg != I915_FENCE_REG_NONE) {
 		I915_WRITE(SNB_DPFC_CTL_SA,