diff mbox

[V2,4/6] ARM: dts: imx6q: add pinctrl for WEIM NOR

Message ID 1369296978-7669-5-git-send-email-b32955@freescale.com (mailing list archive)
State New, archived
Headers show

Commit Message

Huang Shijie May 23, 2013, 8:16 a.m. UTC 
Add a pinctrl for WEIM nor.

Signed-off-by: Huang Shijie <b32955@freescale.com>
---
 arch/arm/boot/dts/imx6q.dtsi |   56 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 56 insertions(+), 0 deletions(-)

Comments

Alexander Shiyan May 23, 2013, 9:14 a.m. UTC | #1 
> Add a pinctrl for WEIM nor.
> 
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   56 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 56 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index ed11bcf..2a6327a 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -323,6 +323,62 @@
>  						>;
>  					};
>  				};
> +
> +				weim {
> +					pinctrl_weim_nor_1: weim_norgrp-1 {

I suggest remove "nor" label here since it can be used for other devices later.

> +						fsl,pins = <
> +							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1

Since driver can support multiple chipselects it would be nice to
define EIM_CSX in other place for possible using other chipselects.

> +							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
> +							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
> +							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
> +
> +							/* data */
> +							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
> +							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
> +							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
> +							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
> +							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
> +							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
> +							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
> +							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
> +							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
> +							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
> +							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
> +							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
> +							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
> +							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
> +							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
> +							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
> +
> +							/* address */
> +							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
> +							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
> +							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
> +							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
> +							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
> +							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
> +							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
> +							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
> +							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
> +							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
> +							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
> +							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
> +							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
> +							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
> +							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
> +							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
> +							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
> +							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
> +							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
> +							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
> +							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
> +							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
> +							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
> +							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
> +						>;
> +					};
> +
> +				};
>  			};
>  		};
>  
> -- 

---
Huang Shijie May 23, 2013, 9:27 a.m. UTC | #2 
? 2013?05?23? 17:14, Alexander Shiyan ??:
> I suggest remove "nor" label here since it can be used for other devices later.
this pinctrl is just for NOR.

If we attach other device to WEIM, it maybe needs other PAD, such as

MX6Q_PAD_EIM_LBA__EIM_LBA_B.  We need to add another pinctrl then.



>> >  +						fsl,pins =<
>> >  +							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
> Since driver can support multiple chipselects it would be nice to
> define EIM_CSX in other place for possible using other chipselects.
>
Ditto.

thanks
Huang Shijie
Alexander Shiyan May 23, 2013, 9:39 a.m. UTC | #3 
> > I suggest remove "nor" label here since it can be used for other devices later.
> this pinctrl is just for NOR.
> 
> If we attach other device to WEIM, it maybe needs other PAD, such as
> MX6Q_PAD_EIM_LBA__EIM_LBA_B. We need to add another pinctrl then.

How we should define CS1 pin in your example for second device?

---
Huang Shijie May 23, 2013, 9:52 a.m. UTC | #4 
? 2013?05?23? 17:39, Alexander Shiyan ??:
> How we should define CS1 pin in your example for second device?
>

But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to 
WEIM.
I do not need to worry about the second device.


If in customer's boards, they connect two devices to the weim.
they should add their own special pinctrl for the two devices, such as 
split out the CS pad.

But for the imx6q{dl}-sabreauto boards, i do not need to do so.




thanks
Huang Shijie
Alexander Shiyan May 23, 2013, 9:55 a.m. UTC | #5 
> > How we should define CS1 pin in your example for second device?
> 
> But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to 
> WEIM.
> I do not need to worry about the second device.

OK, but you add "weim-NOR" to the arch/arm/boot/dts/imx6q.dtsi, not
in imx6qdl-sabreauto.dtsi, so you mean that this definition is generic.
Should it be moved to imx6qdl-sabreauto.dtsi then?

---
Huang Shijie May 24, 2013, 2:41 a.m. UTC | #6 
? 2013?05?23? 17:55, Alexander Shiyan ??:
>>> How we should define CS1 pin in your example for second device?
>> But in the imx6q{dl}-sabreauto boards, we only have the NOR connected to
>> WEIM.
>> I do not need to worry about the second device.
> OK, but you add "weim-NOR" to the arch/arm/boot/dts/imx6q.dtsi, not
> in imx6qdl-sabreauto.dtsi, so you mean that this definition is generic.
> Should it be moved to imx6qdl-sabreauto.dtsi then?
okay. I will split out the CS pad to single pinctrl.

thanks for your review.

Huang Shijie
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ed11bcf..2a6327a 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -323,6 +323,62 @@ 
 						>;
 					};
 				};
+
+				weim {
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+							MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+
+							/* data */
+							MX6Q_PAD_EIM_D16__EIM_DATA16 0xb0b1
+							MX6Q_PAD_EIM_D17__EIM_DATA17 0xb0b1
+							MX6Q_PAD_EIM_D18__EIM_DATA18 0xb0b1
+							MX6Q_PAD_EIM_D19__EIM_DATA19 0xb0b1
+							MX6Q_PAD_EIM_D20__EIM_DATA20 0xb0b1
+							MX6Q_PAD_EIM_D21__EIM_DATA21 0xb0b1
+							MX6Q_PAD_EIM_D22__EIM_DATA22 0xb0b1
+							MX6Q_PAD_EIM_D23__EIM_DATA23 0xb0b1
+							MX6Q_PAD_EIM_D24__EIM_DATA24 0xb0b1
+							MX6Q_PAD_EIM_D25__EIM_DATA25 0xb0b1
+							MX6Q_PAD_EIM_D26__EIM_DATA26 0xb0b1
+							MX6Q_PAD_EIM_D27__EIM_DATA27 0xb0b1
+							MX6Q_PAD_EIM_D28__EIM_DATA28 0xb0b1
+							MX6Q_PAD_EIM_D29__EIM_DATA29 0xb0b1
+							MX6Q_PAD_EIM_D30__EIM_DATA30 0xb0b1
+							MX6Q_PAD_EIM_D31__EIM_DATA31 0xb0b1
+
+							/* address */
+							MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+
+				};
 			};
 		};