diff mbox

PM: Disable usb host HW save and restore

Message ID 1240484331-18722-1-git-send-email-kalle.jokiniemi@digia.com (mailing list archive)
State Accepted
Delegated to: Kevin Hilman
Headers show

Commit Message

Kalle Jokiniemi April 23, 2009, 10:58 a.m. UTC
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.

Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
---
 arch/arm/mach-omap2/powerdomains34xx.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

Comments

Kevin Hilman May 14, 2009, 5:10 p.m. UTC | #1
Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:

> The hardware SAVEANDRESTORE mechanism seems to leave
> USB HOST power domain permanently into active state
> after one transition from off to active state.
> Disabling for now.
>
> Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>

Thanks, pushing to PM branch.

Paul, will you incoporate this into your upstream queue as well?

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/powerdomains34xx.h |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
> index 4dcf94b..aa557b2 100644
> --- a/arch/arm/mach-omap2/powerdomains34xx.h
> +++ b/arch/arm/mach-omap2/powerdomains34xx.h
> @@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = {
>  	.sleepdep_srcs	  = dss_per_usbhost_sleepdeps,
>  	.pwrsts		  = PWRSTS_OFF_RET_ON,
>  	.pwrsts_logic_ret = PWRDM_POWER_RET,
> -	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
> +	/*
> +	 * REVISIT: Enabling usb host save and restore mechanism seems to
> +	 * leave the usb host domain permanently in ACTIVE mode after
> +	 * changing the usb host power domain state from OFF to active once.
> +	 * Disabling for now.
> +	 */
> +	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
>  	.banks		  = 1,
>  	.pwrsts_mem_ret	  = {
>  		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
> -- 
> 1.5.4.3
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Woodruff, Richard May 14, 2009, 5:40 p.m. UTC | #2
> From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> Sent: Thursday, May 14, 2009 12:10 PM
> To: Kalle Jokiniemi

> Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:
>
> > The hardware SAVEANDRESTORE mechanism seems to leave
> > USB HOST power domain permanently into active state
> > after one transition from off to active state.
> > Disabling for now.

Some are is needed around USB host domain handling.  There are a couple errata impacting different chip revs.

Today in the older TI reference code this condition of a stuck on power domain does not happen.  However, we are using a software supervised method to disable the power domain.  May be this code has a bug or the hardware does around auto use for this domain.

You will want TLL or host SAR activated to minimally work around a possible false cold reset issue.  There is a window coming back from OFF where a reset will be thrown.  Enabling SAR conclusively moves the internal window so there is no danger.  The error is fairly easily seen so if you start taking resets know this is likely the root cause.

What Rev of CPU is the issue occurring on?

The USBTLL SAR in 3.0 and before silicon will case a deadlock on 2nd sleep attempt.  On 3.1 and after its fixed.

Regards,
Richard W.
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Kalle Jokiniemi May 15, 2009, 6:44 a.m. UTC | #3
On Thu, 2009-05-14 at 20:40 +0300, Woodruff, Richard wrote:
> > From: Kevin Hilman [mailto:khilman@deeprootsystems.com]
> > Sent: Thursday, May 14, 2009 12:10 PM
> > To: Kalle Jokiniemi
> 
> > Kalle Jokiniemi <kalle.jokiniemi@digia.com> writes:
> >
> > > The hardware SAVEANDRESTORE mechanism seems to leave
> > > USB HOST power domain permanently into active state
> > > after one transition from off to active state.
> > > Disabling for now.
> 
> Some are is needed around USB host domain handling.  There are a
> couple errata impacting different chip revs.
> 
> Today in the older TI reference code this condition of a stuck on
> power domain does not happen.  However, we are using a software
> supervised method to disable the power domain.  May be this code has a
> bug or the hardware does around auto use for this domain.

Yes, usb-host autoidle was enabled when I was digging this issue.

> 
> You will want TLL or host SAR activated to minimally work around a
> possible false cold reset issue.  There is a window coming back from
> OFF where a reset will be thrown.  Enabling SAR conclusively moves the
> internal window so there is no danger.  The error is fairly easily
> seen so if you start taking resets know this is likely the root cause.
> 
> What Rev of CPU is the issue occurring on?

I think the usb-host problem was on ES3.1 at least.

> 
> The USBTLL SAR in 3.0 and before silicon will case a deadlock on 2nd
> sleep attempt.  On 3.1 and after its fixed.

So ES3.0 devices are exposed to the cold reset issue (since USBTLL SAR
is only enabled in ES3.1). Would you suspect that we can enable USB host
SAR, if the AUTOIDLE is turned off? Then we would not need this patch.

- Kalle

> 
> Regards,
> Richard W.

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Woodruff, Richard May 15, 2009, 11:47 a.m. UTC | #4
> > couple errata impacting different chip revs.
> >
> > Today in the older TI reference code this condition of a stuck on
> > power domain does not happen.  However, we are using a software
> > supervised method to disable the power domain.  May be this code has a
> > bug or the hardware does around auto use for this domain.
>
> Yes, usb-host autoidle was enabled when I was digging this issue.

Host domain?  (not host module).

> > The USBTLL SAR in 3.0 and before silicon will case a deadlock on 2nd
> > sleep attempt.  On 3.1 and after its fixed.
>
> So ES3.0 devices are exposed to the cold reset issue (since USBTLL SAR
> is only enabled in ES3.1). Would you suspect that we can enable USB host
> SAR, if the AUTOIDLE is turned off? Then we would not need this patch.

For 3.0 we used a software sar if ohci was in use.  For ehci its not good enough as there is state not accessible by software.

Not as you wrote. I was thinking you need to try to go to idle using CM_CLKSTCTRL_USBHOST = 1.  Not at 0x3 and then waiting for a dependent event to trigger you.  Once your preconditions are met you can initiate and idle ack sequence.

Regards,
Richard W.
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Kalle Jokiniemi May 15, 2009, 1:52 p.m. UTC | #5
On Fri, 2009-05-15 at 14:47 +0300, Woodruff, Richard wrote:
> > > couple errata impacting different chip revs.
> > >
> > > Today in the older TI reference code this condition of a stuck on
> > > power domain does not happen.  However, we are using a software
> > > supervised method to disable the power domain.  May be this code has a
> > > bug or the hardware does around auto use for this domain.
> >
> > Yes, usb-host autoidle was enabled when I was digging this issue.
> 
> Host domain?  (not host module).

OTG_SYSCONFIG.AUTOIDLE was what I meant.

> 
> > > The USBTLL SAR in 3.0 and before silicon will case a deadlock on 2nd
> > > sleep attempt.  On 3.1 and after its fixed.
> >
> > So ES3.0 devices are exposed to the cold reset issue (since USBTLL SAR
> > is only enabled in ES3.1). Would you suspect that we can enable USB host
> > SAR, if the AUTOIDLE is turned off? Then we would not need this patch.
> 
> For 3.0 we used a software sar if ohci was in use.  For ehci its not
> good enough as there is state not accessible by software.

USB is by no means my specialty. That being said, using HW SAR could be
used on ohci as well, right? Like you said: the cold reset issue will
remain, if we don't use HW SAR for either USBTLL or USB HOST. And using
USBTLL is not possible for ES3.0 due to that errata.  

> 
> Not as you wrote. I was thinking you need to try to go to idle using
> CM_CLKSTCTRL_USBHOST = 1.  Not at 0x3 and then waiting for a dependent
> event to trigger you.  Once your preconditions are met you can
> initiate and idle ack sequence.

Ok, now I understand what you meant. I used toggling
"/sys/power/enable_off_mode" to switch the USB HOST power domain state
from RET->OFF->RET->.... Problem was I got RET->OFF->ON->ON->ON....

The resource framework takes care of switching usb-state (with
next_state values and hw automated state transition) in this case. We
would need some special usb sw transition code in resource framework
and/or pm code to make the transitions work for usb host.

- Kalle

> 
> Regards,
> Richard W.

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Rajendra Nayak June 5, 2009, 1:06 p.m. UTC | #6
Kalle,

I just found an issue with the  pwrdm_enable_hdwr_sar function which
would actually leave the SAVEANDRESTORE bit unchanged in the PWSTCTRL
register.
http://marc.info/?l=linux-omap&m=124420689003913&w=2

The issue you were seeing with USBHOST might not really be with enabling the SAR
on USBHOST but something else.

regards,
Rajendra

>-----Original Message-----
>From: linux-omap-owner@vger.kernel.org 
>[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Kalle Jokiniemi
>Sent: Thursday, April 23, 2009 4:29 PM
>To: tony@atomide.com
>Cc: khilman@deeprootsystems.com; paul@pwsan.com; 
>linux-omap@vger.kernel.org; Menon, Nishanth; Woodruff, 
>Richard; Kalle Jokiniemi; Kalle Jokiniemi
>Subject: [PATCH] PM: Disable usb host HW save and restore
>
>The hardware SAVEANDRESTORE mechanism seems to leave
>USB HOST power domain permanently into active state
>after one transition from off to active state.
>Disabling for now.
>
>Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
>---
> arch/arm/mach-omap2/powerdomains34xx.h |    8 +++++++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
>
>diff --git a/arch/arm/mach-omap2/powerdomains34xx.h 
>b/arch/arm/mach-omap2/powerdomains34xx.h
>index 4dcf94b..aa557b2 100644
>--- a/arch/arm/mach-omap2/powerdomains34xx.h
>+++ b/arch/arm/mach-omap2/powerdomains34xx.h
>@@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = {
> 	.sleepdep_srcs	  = dss_per_usbhost_sleepdeps,
> 	.pwrsts		  = PWRSTS_OFF_RET_ON,
> 	.pwrsts_logic_ret = PWRDM_POWER_RET,
>-	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBHOST 
>ctrlr only */
>+	/*
>+	 * REVISIT: Enabling usb host save and restore 
>mechanism seems to
>+	 * leave the usb host domain permanently in ACTIVE mode after
>+	 * changing the usb host power domain state from OFF to 
>active once.
>+	 * Disabling for now.
>+	 */
>+	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for 
>USBHOST ctrlr only */
> 	.banks		  = 1,
> 	.pwrsts_mem_ret	  = {
> 		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
>-- 
>1.5.4.3
>
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diff mbox

Patch

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 4dcf94b..aa557b2 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -338,7 +338,13 @@  static struct powerdomain usbhost_pwrdm = {
 	.sleepdep_srcs	  = dss_per_usbhost_sleepdeps,
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.pwrsts_logic_ret = PWRDM_POWER_RET,
-	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
+	/*
+	 * REVISIT: Enabling usb host save and restore mechanism seems to
+	 * leave the usb host domain permanently in ACTIVE mode after
+	 * changing the usb host power domain state from OFF to active once.
+	 * Disabling for now.
+	 */
+	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
 	.banks		  = 1,
 	.pwrsts_mem_ret	  = {
 		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */