diff mbox

[RFC,5/6] arm64/xen: implement xen_remap on arm64

Message ID 1369930713-6063-5-git-send-email-stefano.stabellini@eu.citrix.com (mailing list archive)
State New, archived
Headers show

Commit Message

Stefano Stabellini May 30, 2013, 4:18 p.m. UTC
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
 arch/arm/include/asm/xen/page.h |    4 ++++
 arch/arm64/include/asm/io.h     |    1 +
 2 files changed, 5 insertions(+), 0 deletions(-)

Comments

Catalin Marinas May 31, 2013, 10:59 a.m. UTC | #1
On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> --- a/arch/arm/include/asm/xen/page.h
> +++ b/arch/arm/include/asm/xen/page.h
> @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
>  	return __set_phys_to_machine(pfn, mfn);
>  }
>  
> +#ifdef CONFIG_ARM64
> +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> +#else
>  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> +#endif

Now I saw the ARM-specific part. Can you not use something like
ioremap_cached() which would give normal cacheable memory (at least on
ARMv7).

>  #endif /* _ASM_ARM_XEN_PAGE_H */
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> index 2e12258..0e9c9ac 100644
> --- a/arch/arm64/include/asm/io.h
> +++ b/arch/arm64/include/asm/io.h
> @@ -228,6 +228,7 @@ extern void __iounmap(volatile void __iomem *addr);
>  #define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
>  #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
>  #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
> +#define PROT_NORMAL		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
>  
>  #define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
>  #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

Of course we need to add ioremap_cached() for arm64 but until now we
didn't need it.
Stefano Stabellini May 31, 2013, 1:21 p.m. UTC | #2
On Fri, 31 May 2013, Catalin Marinas wrote:
> On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > --- a/arch/arm/include/asm/xen/page.h
> > +++ b/arch/arm/include/asm/xen/page.h
> > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> >  	return __set_phys_to_machine(pfn, mfn);
> >  }
> >  
> > +#ifdef CONFIG_ARM64
> > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > +#else
> >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > +#endif
> 
> Now I saw the ARM-specific part. Can you not use something like
> ioremap_cached() which would give normal cacheable memory (at least on
> ARMv7).

No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
needs to be MT_MEMORY. It is used for normal memory pages, not device
memory.
Catalin Marinas May 31, 2013, 2:16 p.m. UTC | #3
On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Catalin Marinas wrote:
> > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > --- a/arch/arm/include/asm/xen/page.h
> > > +++ b/arch/arm/include/asm/xen/page.h
> > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > >  	return __set_phys_to_machine(pfn, mfn);
> > >  }
> > >  
> > > +#ifdef CONFIG_ARM64
> > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > +#else
> > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > +#endif
> > 
> > Now I saw the ARM-specific part. Can you not use something like
> > ioremap_cached() which would give normal cacheable memory (at least on
> > ARMv7).
> 
> No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> needs to be MT_MEMORY. It is used for normal memory pages, not device
> memory.

MT_DEVICE_CACHED is Normal memory for ARMv7.
Stefano Stabellini May 31, 2013, 2:50 p.m. UTC | #4
On Fri, 31 May 2013, Catalin Marinas wrote:
> On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > --- a/arch/arm/include/asm/xen/page.h
> > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > >  	return __set_phys_to_machine(pfn, mfn);
> > > >  }
> > > >  
> > > > +#ifdef CONFIG_ARM64
> > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > +#else
> > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > +#endif
> > > 
> > > Now I saw the ARM-specific part. Can you not use something like
> > > ioremap_cached() which would give normal cacheable memory (at least on
> > > ARMv7).
> > 
> > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > memory.
> 
> MT_DEVICE_CACHED is Normal memory for ARMv7.

I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
same AttrIndx encoding!
In that case yes, I should be able to use it.
I take that I should just implement ioremap_cached on arm64 as well?
Stefano Stabellini May 31, 2013, 3:23 p.m. UTC | #5
On Fri, 31 May 2013, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Catalin Marinas wrote:
> > On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > > --- a/arch/arm/include/asm/xen/page.h
> > > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > > >  	return __set_phys_to_machine(pfn, mfn);
> > > > >  }
> > > > >  
> > > > > +#ifdef CONFIG_ARM64
> > > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > > +#else
> > > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > > +#endif
> > > > 
> > > > Now I saw the ARM-specific part. Can you not use something like
> > > > ioremap_cached() which would give normal cacheable memory (at least on
> > > > ARMv7).
> > > 
> > > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > > memory.
> > 
> > MT_DEVICE_CACHED is Normal memory for ARMv7.
> 
> I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
> same AttrIndx encoding!
> In that case yes, I should be able to use it.
> I take that I should just implement ioremap_cached on arm64 as well?
> 

Should just use MT_MEMORY and call it PROT_NORMAL?

#define PROT_NORMAL     (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
#define ioremap_cached(addr, size)     __ioremap((addr), (size), __pgprot(PROT_NORMAL))
Catalin Marinas May 31, 2013, 3:56 p.m. UTC | #6
On Fri, May 31, 2013 at 04:23:20PM +0100, Stefano Stabellini wrote:
> On Fri, 31 May 2013, Stefano Stabellini wrote:
> > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > On Fri, May 31, 2013 at 02:21:16PM +0100, Stefano Stabellini wrote:
> > > > On Fri, 31 May 2013, Catalin Marinas wrote:
> > > > > On Thu, May 30, 2013 at 05:18:32PM +0100, Stefano Stabellini wrote:
> > > > > > --- a/arch/arm/include/asm/xen/page.h
> > > > > > +++ b/arch/arm/include/asm/xen/page.h
> > > > > > @@ -90,6 +90,10 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
> > > > > >  	return __set_phys_to_machine(pfn, mfn);
> > > > > >  }
> > > > > >  
> > > > > > +#ifdef CONFIG_ARM64
> > > > > > +#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
> > > > > > +#else
> > > > > >  #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
> > > > > > +#endif
> > > > > 
> > > > > Now I saw the ARM-specific part. Can you not use something like
> > > > > ioremap_cached() which would give normal cacheable memory (at least on
> > > > > ARMv7).
> > > > 
> > > > No, I cannot because ioremap_cached uses MT_DEVICE_CACHED, while this
> > > > needs to be MT_MEMORY. It is used for normal memory pages, not device
> > > > memory.
> > > 
> > > MT_DEVICE_CACHED is Normal memory for ARMv7.
> > 
> > I didn't realize that MT_DEVICE_CACHED and MT_MEMORY end up having the
> > same AttrIndx encoding!
> > In that case yes, I should be able to use it.
> > I take that I should just implement ioremap_cached on arm64 as well?
> > 
> 
> Should just use MT_MEMORY and call it PROT_NORMAL?
> 
> #define PROT_NORMAL     (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
> #define ioremap_cached(addr, size)     __ioremap((addr), (size), __pgprot(PROT_NORMAL))

Looks fine.
diff mbox

Patch

diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index cb2fa15..d995ece 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -90,6 +90,10 @@  static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
 	return __set_phys_to_machine(pfn, mfn);
 }
 
+#ifdef CONFIG_ARM64
+#define xen_remap(cookie, size) __ioremap((cookie), (size), __pgprot(PROT_NORMAL))
+#else
 #define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
+#endif
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 2e12258..0e9c9ac 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -228,6 +228,7 @@  extern void __iounmap(volatile void __iomem *addr);
 #define PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
 #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL		(PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
 
 #define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))