| Message ID | 1369139314-3003-4-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 21, 2013 at 03:28:34PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The specs are a bit unclear whether the per-plane trickle feed disable > control exists on VLV. There is another trickle feed disable control > in the MI_ARB register. > > Based on some quick register dumps from Jani's VLV machine, the per-plane > bits don't actually seem to exist, so I'm guessing we should use the > MI_ARB method instead. I think neither. I'm guessing this behaviour is covered by 'Note: On mobile products this bit will be ignored such that Trickle Feed is always disabled.' in the DSP.CNTR spec. And I don't think MI_ARB_STATE is applicable as it wasn't used for the display block VLV was based upon. Being VPN-less I can't actually dig through the VLV bspec to confirm. -Chris
On Tue, Jun 04, 2013 at 03:19:12PM +0100, Chris Wilson wrote: > On Tue, May 21, 2013 at 03:28:34PM +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > The specs are a bit unclear whether the per-plane trickle feed disable > > control exists on VLV. There is another trickle feed disable control > > in the MI_ARB register. > > > > Based on some quick register dumps from Jani's VLV machine, the per-plane > > bits don't actually seem to exist, so I'm guessing we should use the > > MI_ARB method instead. > > I think neither. I'm guessing this behaviour is covered by 'Note: On > mobile products this bit will be ignored such that Trickle Feed is > always disabled.' in the DSP.CNTR spec. And I don't think MI_ARB_STATE > is applicable as it wasn't used for the display block VLV was based > upon. > > Being VPN-less I can't actually dig through the VLV bspec to confirm. The register spec has it, and it's even highlighted so it was apparetnly changed at some point. Also note that the register seems to differ from MI_ARB_STATE by being the non masked type, so clearly someone felt the need to edit it for some reason. The display cluster doc also says that trickle feed is configurable, but doesn't go into any further details on the subject. I guess we should confirm on real hardware whether the bit sticks. I don't remember if I poked Jani to do that since he was a bit busy with other stuff when I made the patch. Anyways, that could give us a hint whether the bit really does something.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 55caedb..942699a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1321,6 +1321,8 @@ #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) #define FW_CSPWRDWNEN (1<<15) +#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) + /* * Palette regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5690b3d..93d13d9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4282,7 +4282,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) static void valleyview_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int pipe; I915_WRITE(WM3_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0); @@ -4359,12 +4358,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); - for_each_pipe(pipe) { - I915_WRITE(DSPCNTR(pipe), - I915_READ(DSPCNTR(pipe)) | - DISPPLANE_TRICKLE_FEED_DISABLE); - intel_flush_display_plane(dev_priv, pipe); - } + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));