| Message ID | 1241681366-21094-1-git-send-email-santosh.shilimkar@ti.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
* Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 > SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC > with GIC used for interrupt handling and SCU for cache coherency. > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > --- > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > arch/arm/mach-omap2/omap-smp.c | 238 +++++++++++++++++++++++++++++++++ > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > 4 files changed, 371 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > create mode 100644 arch/arm/mach-omap2/omap-smp.c > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > create mode 100644 arch/arm/plat-omap/include/mach/smp.h <snip snip> > --- /dev/null > +++ b/arch/arm/mach-omap2/omap-smp.c > @@ -0,0 +1,238 @@ > +/* > + * OMAP4 SMP source file. It contains platform specific fucntions > + * needed for the linux smp kernel. > + * > + * Copyright (C) 2009 Texas Instruments, Inc. > + * > + * Author: > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * Platform file needed for the OMAP4 SMP. This file is based on arm > + * realview smp platform. > + * * Copyright (c) 2002 ARM Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/init.h> > +#include <linux/errno.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/jiffies.h> > +#include <linux/smp.h> > +#include <linux/io.h> > + > +#include <asm/cacheflush.h> > +#include <mach/scu.h> > +#include <mach/hardware.h> > +#include <asm/mach-types.h> > + > +/* Registers used for communicating startup information */ > +#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > +#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > + > +/* FIXME: Move to a common header file */ > +extern void omap_secondary_startup(void); How about move this to cpu.h? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
One more comment on this patch below. * Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 > SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC > with GIC used for interrupt handling and SCU for cache coherency. > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > --- > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > arch/arm/mach-omap2/omap-smp.c | 238 +++++++++++++++++++++++++++++++++ > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > 4 files changed, 371 insertions(+), 0 deletions(-) > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > create mode 100644 arch/arm/mach-omap2/omap-smp.c > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > create mode 100644 arch/arm/plat-omap/include/mach/smp.h > > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c > new file mode 100644 > index 0000000..1d18acb > --- /dev/null > +++ b/arch/arm/mach-omap2/omap-smp.c <snip snip> > +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned long timeout; > + > + /* > + * Set synchronisation state between this boot processor > + * and the secondary one > + */ > + spin_lock(&boot_lock); > + > + /* > + * The secondary processor is waiting for an event to come out of > + * wfe. Release it, then wait for it to flag that it has been > + * released by resetting cpu_release. > + * > + * Singal the ROM code that the secondary core can be released > + */ > + cpu_release = cpu; > + __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); > + flush_cache_all(); > + /* > + * Send a 'sev' to wake the secondary core again because > + * ROM code will put core in WFE till the cpu_release > + * flag is set. > + */ > + set_event(); > + mb(); > + > + timeout = jiffies + (1 * HZ); > + while (time_before(jiffies, timeout)) { > + smp_rmb(); > + if (cpu_release == -1) > + break; > + > + udelay(10); > + } > + > + /* > + * Now the secondary core is starting up let it run its > + * calibrations, then wait for it to finish > + */ > + spin_unlock(&boot_lock); > + > + return cpu_release != -1 ? -ENOSYS : 0; > +} The "Singal" should be "Signal" above :) Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Tony Lindgren [mailto:tony@atomide.com] > Sent: Friday, May 08, 2009 2:17 AM > To: Shilimkar, Santosh > Cc: linux-arm-kernel@lists.arm.linux.org.uk; > linux-omap@vger.kernel.org > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > * Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > > This patch adds SMP platform files support for OMAP4430SDP. > TI's OMAP4430 > > SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC > > with GIC used for interrupt handling and SCU for cache coherency. > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > --- > > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > > arch/arm/mach-omap2/omap-smp.c | 238 > +++++++++++++++++++++++++++++++++ > > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > > 4 files changed, 371 insertions(+), 0 deletions(-) > > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > > create mode 100644 arch/arm/mach-omap2/omap-smp.c > > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > > create mode 100644 arch/arm/plat-omap/include/mach/smp.h > > <snip snip> > > > --- /dev/null > > +++ b/arch/arm/mach-omap2/omap-smp.c > > @@ -0,0 +1,238 @@ > > +/* > > + * OMAP4 SMP source file. It contains platform specific fucntions > > + * needed for the linux smp kernel. > > + * > > + * Copyright (C) 2009 Texas Instruments, Inc. > > + * > > + * Author: > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > + * > > + * Platform file needed for the OMAP4 SMP. This file is > based on arm > > + * realview smp platform. > > + * * Copyright (c) 2002 ARM Limited. > > + * > > + * This program is free software; you can redistribute it > and/or modify > > + * it under the terms of the GNU General Public License > version 2 as > > + * published by the Free Software Foundation. > > + */ > > +#include <linux/init.h> > > +#include <linux/errno.h> > > +#include <linux/delay.h> > > +#include <linux/device.h> > > +#include <linux/jiffies.h> > > +#include <linux/smp.h> > > +#include <linux/io.h> > > + > > +#include <asm/cacheflush.h> > > +#include <mach/scu.h> > > +#include <mach/hardware.h> > > +#include <asm/mach-types.h> > > + > > +/* Registers used for communicating startup information */ > > +#define OMAP4_AUXCOREBOOT_REG0 > (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > > +#define OMAP4_AUXCOREBOOT_REG1 > (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > > + > > +/* FIXME: Move to a common header file */ > > +extern void omap_secondary_startup(void); > > How about move this to cpu.h? Possible. The thing is this functions should be available only for OMAP4 SMP. We may need #ifdef ARCH_OMAP4. Is that ok ? -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
---- Original Message ----- From: "Santosh Shilimkar" <santosh.shilimkar@ti.com> Subject: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > diff --git a/arch/arm/mach-omap2/omap-headsmp.S > b/arch/arm/mach-omap2/omap-headsmp.S > new file mode 100644 > index 0000000..0afe039 > --- /dev/null > +++ b/arch/arm/mach-omap2/omap-headsmp.S > @@ -0,0 +1,49 @@ > +/* > + * Secondary CPU startup routine source file. > + * > + * Copyright (C) 2009 Texas Instruments, Inc. > + * > + * Author: > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * Interface functions needed for the SMP. This file is based on arm > + * realview smp platform. > + * Copyright (c) 2003 ARM Limited. > + * > + * This program is free software,you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/linkage.h> > +#include <linux/init.h> > + > + __INIT > + > +/* > + * OMAP4 specific entry point for secondary CPU to jump from ROM > + * code. This routine also provides a holding flag into which > + * secondary core is held until we're ready for it to initialise. > + * The primary core will update the this flag using a hardware > + * register AuxCoreBoot1. > + */ Is initialization done by u-boot like icache_enable taken care somewhere for the secondary cpu. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: V, Hemanth > Sent: Friday, May 08, 2009 11:16 AM > To: Shilimkar, Santosh; linux-arm-kernel@lists.arm.linux.org.uk > Cc: linux-omap@vger.kernel.org > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > ---- Original Message ----- > From: "Santosh Shilimkar" <santosh.shilimkar@ti.com> > Subject: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > diff --git a/arch/arm/mach-omap2/omap-headsmp.S > > b/arch/arm/mach-omap2/omap-headsmp.S > > new file mode 100644 > > index 0000000..0afe039 > > --- /dev/null > > +++ b/arch/arm/mach-omap2/omap-headsmp.S > > @@ -0,0 +1,49 @@ > > +/* > > + * Secondary CPU startup routine source file. > > + * > > + * Copyright (C) 2009 Texas Instruments, Inc. > > + * > > + * Author: > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > + * > > + * Interface functions needed for the SMP. This file is > based on arm > > + * realview smp platform. > > + * Copyright (c) 2003 ARM Limited. > > + * > > + * This program is free software,you can redistribute it > and/or modify > > + * it under the terms of the GNU General Public License > version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#include <linux/linkage.h> > > +#include <linux/init.h> > > + > > + __INIT > > + > > +/* > > + * OMAP4 specific entry point for secondary CPU to jump from ROM > > + * code. This routine also provides a holding flag into which > > + * secondary core is held until we're ready for it to initialise. > > + * The primary core will update the this flag using a hardware > > + * register AuxCoreBoot1. > > + */ > > Is initialization done by u-boot like icache_enable taken > care somewhere > for the secondary cpu. U-boot has no knowledge of secondary CPUs. Kernel takes care of it with help of ROM code.-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
----- Original Message ----- From: "Shilimkar, Santosh" <santosh.shilimkar@ti.com> To: "V, Hemanth" <hemanthv@ti.com>; <linux-arm-kernel@lists.arm.linux.org.uk> Cc: <linux-omap@vger.kernel.org> Sent: Friday, May 08, 2009 11:18 AM Subject: RE: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > -----Original Message----- > From: V, Hemanth > Sent: Friday, May 08, 2009 11:16 AM > To: Shilimkar, Santosh; linux-arm-kernel@lists.arm.linux.org.uk > Cc: linux-omap@vger.kernel.org > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > ---- Original Message ----- > From: "Santosh Shilimkar" <santosh.shilimkar@ti.com> > Subject: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > diff --git a/arch/arm/mach-omap2/omap-headsmp.S > > b/arch/arm/mach-omap2/omap-headsmp.S > > new file mode 100644 > > index 0000000..0afe039 > > --- /dev/null > > +++ b/arch/arm/mach-omap2/omap-headsmp.S > > @@ -0,0 +1,49 @@ > > +/* > > + * Secondary CPU startup routine source file. > > + * > > + * Copyright (C) 2009 Texas Instruments, Inc. > > + * > > + * Author: > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > + * > > + * Interface functions needed for the SMP. This file is > based on arm > > + * realview smp platform. > > + * Copyright (c) 2003 ARM Limited. > > + * > > + * This program is free software,you can redistribute it > and/or modify > > + * it under the terms of the GNU General Public License > version 2 as > > + * published by the Free Software Foundation. > > + */ > > + > > +#include <linux/linkage.h> > > +#include <linux/init.h> > > + > > + __INIT > > + > > +/* > > + * OMAP4 specific entry point for secondary CPU to jump from ROM > > + * code. This routine also provides a holding flag into which > > + * secondary core is held until we're ready for it to initialise. > > + * The primary core will update the this flag using a hardware > > + * register AuxCoreBoot1. > > + */ > > Is initialization done by u-boot like icache_enable taken > care somewhere > for the secondary cpu. >>U-boot has no knowledge of secondary CPUs. Kernel takes care of it with >>help of ROM code. For my information could you pl point to the routine which does this, i.e enable instruction cache on the secondary cpu. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> Subject: RE: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > -----Original Message----- > > From: V, Hemanth > > Sent: Friday, May 08, 2009 11:16 AM > > To: Shilimkar, Santosh; linux-arm-kernel@lists.arm.linux.org.uk > > Cc: linux-omap@vger.kernel.org > > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > >>U-boot has no knowledge of secondary CPUs. Kernel takes > care of it with > >>help of ROM code. > > For my information could you pl point to the routine which > does this, i.e > enable instruction cache on the secondary cpu. This is done using __enable_mmu in head.S. Bye the way even if the u-boot don't enable I-cache , D-caches, kernel does that anyways depending on settings.-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
* Shilimkar, Santosh <santosh.shilimkar@ti.com> [090507 22:10]: > > -----Original Message----- > > From: Tony Lindgren [mailto:tony@atomide.com] > > Sent: Friday, May 08, 2009 2:17 AM > > To: Shilimkar, Santosh > > Cc: linux-arm-kernel@lists.arm.linux.org.uk; > > linux-omap@vger.kernel.org > > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > * Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > > > This patch adds SMP platform files support for OMAP4430SDP. > > TI's OMAP4430 > > > SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC > > > with GIC used for interrupt handling and SCU for cache coherency. > > > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > > --- > > > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > > > arch/arm/mach-omap2/omap-smp.c | 238 > > +++++++++++++++++++++++++++++++++ > > > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > > > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > > > 4 files changed, 371 insertions(+), 0 deletions(-) > > > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > > > create mode 100644 arch/arm/mach-omap2/omap-smp.c > > > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > > > create mode 100644 arch/arm/plat-omap/include/mach/smp.h > > > > <snip snip> > > > > > --- /dev/null > > > +++ b/arch/arm/mach-omap2/omap-smp.c > > > @@ -0,0 +1,238 @@ > > > +/* > > > + * OMAP4 SMP source file. It contains platform specific fucntions > > > + * needed for the linux smp kernel. > > > + * > > > + * Copyright (C) 2009 Texas Instruments, Inc. > > > + * > > > + * Author: > > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > > + * > > > + * Platform file needed for the OMAP4 SMP. This file is > > based on arm > > > + * realview smp platform. > > > + * * Copyright (c) 2002 ARM Limited. > > > + * > > > + * This program is free software; you can redistribute it > > and/or modify > > > + * it under the terms of the GNU General Public License > > version 2 as > > > + * published by the Free Software Foundation. > > > + */ > > > +#include <linux/init.h> > > > +#include <linux/errno.h> > > > +#include <linux/delay.h> > > > +#include <linux/device.h> > > > +#include <linux/jiffies.h> > > > +#include <linux/smp.h> > > > +#include <linux/io.h> > > > + > > > +#include <asm/cacheflush.h> > > > +#include <mach/scu.h> > > > +#include <mach/hardware.h> > > > +#include <asm/mach-types.h> > > > + > > > +/* Registers used for communicating startup information */ > > > +#define OMAP4_AUXCOREBOOT_REG0 > > (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > > > +#define OMAP4_AUXCOREBOOT_REG1 > > (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > > > + > > > +/* FIXME: Move to a common header file */ > > > +extern void omap_secondary_startup(void); > > > > How about move this to cpu.h? > > Possible. The thing is this functions should be available only for OMAP4 SMP. We may need #ifdef ARCH_OMAP4. Is that ok ? Please rathar have a ifdef section in cpu.h for CONFIG_SMP. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: linux-omap-owner@vger.kernel.org > [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Tony Lindgren > Sent: Friday, May 08, 2009 8:48 PM > To: Shilimkar, Santosh > Cc: linux-arm-kernel@lists.arm.linux.org.uk; > linux-omap@vger.kernel.org > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [090507 22:10]: > > > -----Original Message----- > > > From: Tony Lindgren [mailto:tony@atomide.com] > > > Sent: Friday, May 08, 2009 2:17 AM > > > To: Shilimkar, Santosh > > > Cc: linux-arm-kernel@lists.arm.linux.org.uk; > > > linux-omap@vger.kernel.org > > > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > > > > > * Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > > > > This patch adds SMP platform files support for OMAP4430SDP. > > > TI's OMAP4430 > > > > SOC is based on ARM Cortex-A9 SMP architecture. It's a > dual core SOC > > > > with GIC used for interrupt handling and SCU for cache > coherency. > > > > > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > > > --- > > > > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > > > > arch/arm/mach-omap2/omap-smp.c | 238 > > > +++++++++++++++++++++++++++++++++ > > > > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > > > > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > > > > 4 files changed, 371 insertions(+), 0 deletions(-) > > > > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > > > > create mode 100644 arch/arm/mach-omap2/omap-smp.c > > > > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > > > > create mode 100644 arch/arm/plat-omap/include/mach/smp.h > > > > > > <snip snip> > > > > > > > --- /dev/null > > > > +++ b/arch/arm/mach-omap2/omap-smp.c > > > > @@ -0,0 +1,238 @@ > > > > +/* > > > > + * OMAP4 SMP source file. It contains platform > specific fucntions > > > > + * needed for the linux smp kernel. > > > > + * > > > > + * Copyright (C) 2009 Texas Instruments, Inc. > > > > + * > > > > + * Author: > > > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > > > + * > > > > + * Platform file needed for the OMAP4 SMP. This file is > > > based on arm > > > > + * realview smp platform. > > > > + * * Copyright (c) 2002 ARM Limited. > > > > + * > > > > + * This program is free software; you can redistribute it > > > and/or modify > > > > + * it under the terms of the GNU General Public License > > > version 2 as > > > > + * published by the Free Software Foundation. > > > > + */ > > > > +#include <linux/init.h> > > > > +#include <linux/errno.h> > > > > +#include <linux/delay.h> > > > > +#include <linux/device.h> > > > > +#include <linux/jiffies.h> > > > > +#include <linux/smp.h> > > > > +#include <linux/io.h> > > > > + > > > > +#include <asm/cacheflush.h> > > > > +#include <mach/scu.h> > > > > +#include <mach/hardware.h> > > > > +#include <asm/mach-types.h> > > > > + > > > > +/* Registers used for communicating startup information */ > > > > +#define OMAP4_AUXCOREBOOT_REG0 > > > (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > > > > +#define OMAP4_AUXCOREBOOT_REG1 > > > (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > > > > + > > > > +/* FIXME: Move to a common header file */ > > > > +extern void omap_secondary_startup(void); > > > > > > How about move this to cpu.h? > > > > Possible. The thing is this functions should be available > only for OMAP4 SMP. We may need #ifdef ARCH_OMAP4. Is that ok ? > > Please rathar have a ifdef section in cpu.h for CONFIG_SMP. Perfect !! Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Tony, Any comments on this patch. http://patchwork.kernel.org/patch/19161/ Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Santosh, Where you will be defining INT_24XX_UART1_IRQ, INT_24XX_UART1_IRQ and INT_24XX_UART3_IRQ ? Is it in include/asm-arm/arch-omap/serial.h?
On Thu, May 07, 2009 at 12:59:24PM +0530, Santosh Shilimkar wrote: > +/* > + * OMAP4 specific entry point for secondary CPU to jump from ROM > + * code. This routine also provides a holding flag into which > + * secondary core is held until we're ready for it to initialise. > + * The primary core will update the this flag using a hardware > + * register AuxCoreBoot1. However, it's actually using the 'cpu_release' variable rather than the AuxCoreBoot1 register. Maybe the comment needs updating, or the code needs fixing? > + */ > +ENTRY(omap_secondary_startup) > + mrc p15, 0, r0, c0, c0, 5 > + and r0, r0, #15 > + adr r4, 1f > + ldmia r4, {r5, r6} > + sub r4, r4, r5 > + add r6, r6, r4 > +hold: ldr r7, [r6] @ read from AuxCoreBoot1 > + cmp r7, r0 > + bne hold > + > + /* > + * we've been released from the holding pen: secondary_stack > + * should now contain the SVC stack for this core > + */ > + b secondary_startup > + > +1: .long . > + .long cpu_release > + > diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c > new file mode 100644 > index 0000000..1d18acb > --- /dev/null > +++ b/arch/arm/mach-omap2/omap-smp.c > @@ -0,0 +1,238 @@ > +/* > + * OMAP4 SMP source file. It contains platform specific fucntions > + * needed for the linux smp kernel. > + * > + * Copyright (C) 2009 Texas Instruments, Inc. > + * > + * Author: > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * Platform file needed for the OMAP4 SMP. This file is based on arm > + * realview smp platform. > + * * Copyright (c) 2002 ARM Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/init.h> > +#include <linux/errno.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/jiffies.h> > +#include <linux/smp.h> > +#include <linux/io.h> > + > +#include <asm/cacheflush.h> > +#include <mach/scu.h> > +#include <mach/hardware.h> > +#include <asm/mach-types.h> > + > +/* Registers used for communicating startup information */ > +#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > +#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > + > +/* FIXME: Move to a common header file */ > +extern void omap_secondary_startup(void); > + > +/* > + * Control for which core is the next to come out of the secondary > + * boot "Auxcontrol_register" > + */ > +int __cpuinitdata cpu_release = -1; > + > +/* > + * Setup the SCU > + */ > +static void scu_enable(void) > +{ > + u32 scu_ctrl; > + void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; > + > + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); > + scu_ctrl |= 1; > + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); > +} > + > +/* > + * Use SCU config register to count number of cores > + */ > +static unsigned int __init get_core_count(void) > +{ > + unsigned int ncores; > + void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; > + > + if (scu_base) { > + ncores = __raw_readl(scu_base + SCU_CONFIG); > + ncores = (ncores & 0x03) + 1; > + } else { > + ncores = 1; Too many tabs. > + } > + > + return ncores; > +} > + > +static DEFINE_SPINLOCK(boot_lock); > + > +void __cpuinit platform_secondary_init(unsigned int cpu) > +{ > + trace_hardirqs_off(); > + > + /* > + * If any interrupts are already enabled for the primary > + * core (e.g. timer irq), then they will not have been enabled > + * for us: do so > + */ > + > + gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); > + > + /* > + * Let the primary processor know we're out of the > + * pen, then head off into the C entry point > + */ > + cpu_release = -1; > + smp_wmb(); > + > + /* > + * Synchronise with the boot thread. > + */ > + spin_lock(&boot_lock); > + spin_unlock(&boot_lock); > +} > + > +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) > +{ > + unsigned long timeout; > + > + /* > + * Set synchronisation state between this boot processor > + * and the secondary one > + */ > + spin_lock(&boot_lock); > + > + /* > + * The secondary processor is waiting for an event to come out of > + * wfe. Release it, then wait for it to flag that it has been > + * released by resetting cpu_release. > + * > + * Singal the ROM code that the secondary core can be released > + */ > + cpu_release = cpu; > + __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); > + flush_cache_all(); > + /* > + * Send a 'sev' to wake the secondary core again because > + * ROM code will put core in WFE till the cpu_release > + * flag is set. Not sure this comment is accurate. Surely the ROM code doesn't know about our own cpu_release flag. > + */ > + set_event(); > + mb(); > + > + timeout = jiffies + (1 * HZ); > + while (time_before(jiffies, timeout)) { > + smp_rmb(); > + if (cpu_release == -1) > + break; > + > + udelay(10); > + } > + > + /* > + * Now the secondary core is starting up let it run its > + * calibrations, then wait for it to finish > + */ > + spin_unlock(&boot_lock); > + > + return cpu_release != -1 ? -ENOSYS : 0; > +} > + > +static void __init wakeup_secondary(void) > +{ > + > + /* cpu is not to be released from the hold yet */ > + cpu_release = -1; > + > + /* > + * write the address of secondary startup into the system-wide > + * AuxCoreBoot0 where ROM code will jump and start executing > + * on secondary core > + */ > + __raw_writel(virt_to_phys(omap_secondary_startup), \ > + OMAP4_AUXCOREBOOT_REG0); > + /* > + * Send a 'sev' to wake the secondary core from WFE. > + */ > + set_event(); > + mb(); > +} > + > +/* > + * Initialise the CPU possible map early - this describes the CPUs > + * which may be present or become present in the system. > + */ > +void __init smp_init_cpus(void) > +{ > + unsigned int i, ncores = get_core_count(); > + > + for (i = 0; i < ncores; i++) > + cpu_set(i, cpu_possible_map); > +} > + > +void __init smp_prepare_cpus(unsigned int max_cpus) > +{ > + unsigned int ncores = get_core_count(); > + unsigned int cpu = smp_processor_id(); > + int i; > + > + /* sanity check */ > + if (ncores == 0) { > + printk(KERN_ERR > + "OMAP4: strange core count of 0? Default to 1\n"); > + ncores = 1; > + } > + > + if (ncores > num_possible_cpus()) { > + printk(KERN_WARNING > + "OMAP4: no. of cores (%d) greater than configured " > + "maximum of %d - clipping\n", > + ncores, num_possible_cpus()); > + ncores = num_possible_cpus(); > + } > + smp_store_cpu_info(cpu); > + > + /* > + * are we trying to boot more cores than exist? > + */ > + if (max_cpus > ncores) > + max_cpus = ncores; > + > +#ifdef CONFIG_LOCAL_TIMERS > + /* > + * Enable the local timer for primary CPU. If the device is > + * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in > + * omap_timer_init > + */ > + local_timer_setup(); > +#endif > + > + /* > + * Initialise the present map, which describes the set of CPUs > + * actually populated at the present time. > + */ > + for (i = 0; i < max_cpus; i++) > + cpu_set(i, cpu_present_map); > + > + /* > + * Initialise the SCU and wake up the secondary core using > + * wakeup_secondary(). > + */ > + if (max_cpus > 1) { > + scu_enable(); > + /* > + * Ensure that the data accessed by CPU0 before the SCU was > + * initialised is visible to CPU1. > + */ > + flush_cache_all(); > + wakeup_secondary(); > + } > +} > diff --git a/arch/arm/plat-omap/include/mach/scu.h b/arch/arm/plat-omap/include/mach/scu.h > new file mode 100644 > index 0000000..2ee6660 > --- /dev/null > +++ b/arch/arm/plat-omap/include/mach/scu.h > @@ -0,0 +1,28 @@ > +/* > + * SCU regsiter header. > + * > + * Copyright (C) 2009 Texas Instruments, Inc. > + * > + * > + * Author: > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * Snoop Control Unit Registers. This file is based on arm > + * realview smp platform. > + * Copyright (c) 2003 ARM Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#ifndef __OMAP_ARCH_SCU_H > +#define __OMAP_ARCH_SCU_H > +/* > + * SCU registers > + */ > +#define SCU_CTRL 0x00 > +#define SCU_CONFIG 0x04 > +#define SCU_CPU_STATUS 0x08 > +#define SCU_INVALIDATE 0x0c > + > +#endif > diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h > new file mode 100644 > index 0000000..b6a3e67 > --- /dev/null > +++ b/arch/arm/plat-omap/include/mach/smp.h > @@ -0,0 +1,56 @@ > +/* > + * OMAP4 machine specific smp.h > + * > + * Copyright (C) 2009 Texas Instruments, Inc. > + * > + * Author: > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > + * > + * Interface functions needed for the SMP. This file is based on arm > + * realview smp platform. > + * Copyright (c) 2003 ARM Limited. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#ifndef OMAP_ARCH_SMP_H > +#define OMAP_ARCH_SMP_H > + > + > +#include <asm/hardware/gic.h> > + > +/* > + * set_event() is used to wake up secondary core from wfe using sev. ROM > + * code puts the second core into wfe(standby). > + * > + */ > + #define set_event() __asm__ __volatile__ ("sev" : : : "memory") > + > +/* > + * We use Soft IRQ1 as the IPI > + */ > +static inline void smp_cross_call(cpumask_t callmap) > +{ > + gic_raise_softirq(callmap, 1); > +} > + > +/* > + * Can be useful for WFI boot strategy. > + */ > +static inline void smp_cross_call_done(cpumask_t callmap) > +{ > +} > + > +/* > + * Read MPIDR: Multiprocessor affinity register > + */ > +#define hard_smp_processor_id() \ > + ({ \ > + unsigned int cpunum; \ > + __asm__("mrc p15, 0, %0, c0, c0, 5" \ > + : "=r" (cpunum)); \ > + cpunum &= 0x0F; \ > + }) > + > +#endif > -- > 1.5.4.7 > > > ------------------------------------------------------------------- > List admin: http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm-kernel > FAQ: http://www.arm.linux.org.uk/mailinglists/faq.php > Etiquette: http://www.arm.linux.org.uk/mailinglists/etiquette.php -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, May 07, 2009 at 01:46:54PM -0700, Tony Lindgren wrote: > * Santosh Shilimkar <santosh.shilimkar@ti.com> [090507 00:29]: > > This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 > > SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC > > with GIC used for interrupt handling and SCU for cache coherency. > > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > > --- > > arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ > > arch/arm/mach-omap2/omap-smp.c | 238 +++++++++++++++++++++++++++++++++ > > arch/arm/plat-omap/include/mach/scu.h | 28 ++++ > > arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ > > 4 files changed, 371 insertions(+), 0 deletions(-) > > create mode 100644 arch/arm/mach-omap2/omap-headsmp.S > > create mode 100644 arch/arm/mach-omap2/omap-smp.c > > create mode 100644 arch/arm/plat-omap/include/mach/scu.h > > create mode 100644 arch/arm/plat-omap/include/mach/smp.h > > <snip snip> > > > --- /dev/null > > +++ b/arch/arm/mach-omap2/omap-smp.c > > @@ -0,0 +1,238 @@ > > +/* > > + * OMAP4 SMP source file. It contains platform specific fucntions > > + * needed for the linux smp kernel. > > + * > > + * Copyright (C) 2009 Texas Instruments, Inc. > > + * > > + * Author: > > + * Santosh Shilimkar <santosh.shilimkar@ti.com> > > + * > > + * Platform file needed for the OMAP4 SMP. This file is based on arm > > + * realview smp platform. > > + * * Copyright (c) 2002 ARM Limited. > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + */ > > +#include <linux/init.h> > > +#include <linux/errno.h> > > +#include <linux/delay.h> > > +#include <linux/device.h> > > +#include <linux/jiffies.h> > > +#include <linux/smp.h> > > +#include <linux/io.h> > > + > > +#include <asm/cacheflush.h> > > +#include <mach/scu.h> > > +#include <mach/hardware.h> > > +#include <asm/mach-types.h> > > + > > +/* Registers used for communicating startup information */ > > +#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) > > +#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) > > + > > +/* FIXME: Move to a common header file */ > > +extern void omap_secondary_startup(void); > > How about move this to cpu.h? No, it doesn't make sense there. mach/smp.h would be a far better choice. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, May 08, 2009 at 12:27:33PM +0530, Shilimkar, Santosh wrote: > This is done using __enable_mmu in head.S. Bye the way even if the > u-boot don't enable I-cache , D-caches, kernel does that anyways > depending on settings. uboot should not be calling the kernel with caches enabled. This is well documented. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Saturday, May 16, 2009 3:59 PM > To: Shilimkar, Santosh > Cc: linux-arm-kernel@lists.arm.linux.org.uk; > linux-omap@vger.kernel.org > Subject: Re: [PATCH 1/3] OMAP4: SMP: Add OMAP4430 SMP board files > > On Thu, May 07, 2009 at 12:59:24PM +0530, Santosh Shilimkar wrote: > > +/* > > + * OMAP4 specific entry point for secondary CPU to jump from ROM > > + * code. This routine also provides a holding flag into which > > + * secondary core is held until we're ready for it to initialise. > > + * The primary core will update the this flag using a hardware > > + * register AuxCoreBoot1. > > However, it's actually using the 'cpu_release' variable rather than > the AuxCoreBoot1 register. Maybe the comment needs updating, or the > code needs fixing? I planned update this bit later. AuxCoreBoot1 would be used instead of variable cpu_release Will add couple of FIXME comments here. > > + */ > > +ENTRY(omap_secondary_startup) > > + mrc p15, 0, r0, c0, c0, 5 > > + and r0, r0, #15 > > + adr r4, 1f > > + ldmia r4, {r5, r6} > > + sub r4, r4, r5 > > + add r6, r6, r4 > > +hold: ldr r7, [r6] @ read from AuxCoreBoot1 > > + cmp r7, r0 > > + bne hold > > + > > + /* > > + * we've been released from the holding pen: secondary_stack > > + * should now contain the SVC stack for this core > > + */ > > + b secondary_startup > > + > > +1: .long . > > + .long cpu_release > > + > > diff --git a/arch/arm/mach-omap2/omap-smp.c > b/arch/arm/mach-omap2/omap-smp.c > > new file mode 100644 > > index 0000000..1d18acb > > --- /dev/null > > +++ b/arch/arm/mach-omap2/omap-smp.c > > @@ -0,0 +1,238 @@ > > +int __cpuinit boot_secondary(unsigned int cpu, struct > task_struct *idle) > > +{ > > + unsigned long timeout; > > + > > + /* > > + * Set synchronisation state between this boot processor > > + * and the secondary one > > + */ > > + spin_lock(&boot_lock); > > + > > + /* > > + * The secondary processor is waiting for an event to > come out of > > + * wfe. Release it, then wait for it to flag that it has been > > + * released by resetting cpu_release. > > + * > > + * Singal the ROM code that the secondary core can be released > > + */ > > + cpu_release = cpu; > > + __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); > > + flush_cache_all(); > > + /* > > + * Send a 'sev' to wake the secondary core again because > > + * ROM code will put core in WFE till the cpu_release > > + * flag is set. > > Not sure this comment is accurate. Surely the ROM code doesn't know > about our own cpu_release flag. Should be some thing like this-- >ROM code will put secondary core in WFE till we flag it using the AuxCoreBoot1 register to bring it up. > > -- > > 1.5.4.7 Regards, Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
* Shilimkar, Santosh <santosh.shilimkar@ti.com> [090513 07:53]: > Tony, > Any comments on this patch. > http://patchwork.kernel.org/patch/19161/ We should just set the interrupts etc dynamically using the cpu_is_omapXXXX() functions. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Tony Lindgren [mailto:tony@atomide.com] > Sent: Tuesday, May 19, 2009 3:16 AM > To: Shilimkar, Santosh > Cc: linux-omap@vger.kernel.org > Subject: Re: [PATCH] OMAP: Remove IRQ hardcoding from serial.c > > * Shilimkar, Santosh <santosh.shilimkar@ti.com> [090513 07:53]: > > Tony, > > Any comments on this patch. > > http://patchwork.kernel.org/patch/19161/ > > We should just set the interrupts etc dynamically using the > cpu_is_omapXXXX() functions. That's indeed a good idea. But then are we going to remove this information from platform structures. If not then hardcoding is still bad and should be removed. Regards, Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S new file mode 100644 index 0000000..0afe039 --- /dev/null +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -0,0 +1,49 @@ +/* + * Secondary CPU startup routine source file. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Interface functions needed for the SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software,you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * OMAP4 specific entry point for secondary CPU to jump from ROM + * code. This routine also provides a holding flag into which + * secondary core is held until we're ready for it to initialise. + * The primary core will update the this flag using a hardware + * register AuxCoreBoot1. + */ +ENTRY(omap_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +hold: ldr r7, [r6] @ read from AuxCoreBoot1 + cmp r7, r0 + bne hold + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + +1: .long . + .long cpu_release + diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c new file mode 100644 index 0000000..1d18acb --- /dev/null +++ b/arch/arm/mach-omap2/omap-smp.c @@ -0,0 +1,238 @@ +/* + * OMAP4 SMP source file. It contains platform specific fucntions + * needed for the linux smp kernel. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Platform file needed for the OMAP4 SMP. This file is based on arm + * realview smp platform. + * * Copyright (c) 2002 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <mach/scu.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +/* Registers used for communicating startup information */ +#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) +#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) + +/* FIXME: Move to a common header file */ +extern void omap_secondary_startup(void); + +/* + * Control for which core is the next to come out of the secondary + * boot "Auxcontrol_register" + */ +int __cpuinitdata cpu_release = -1; + +/* + * Setup the SCU + */ +static void scu_enable(void) +{ + u32 scu_ctrl; + void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; + + scu_ctrl = __raw_readl(scu_base + SCU_CTRL); + scu_ctrl |= 1; + __raw_writel(scu_ctrl, scu_base + SCU_CTRL); +} + +/* + * Use SCU config register to count number of cores + */ +static unsigned int __init get_core_count(void) +{ + unsigned int ncores; + void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; + + if (scu_base) { + ncores = __raw_readl(scu_base + SCU_CONFIG); + ncores = (ncores & 0x03) + 1; + } else { + ncores = 1; + } + + return ncores; +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + + /* + * If any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + + gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); + + /* + * Let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + cpu_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting for an event to come out of + * wfe. Release it, then wait for it to flag that it has been + * released by resetting cpu_release. + * + * Singal the ROM code that the secondary core can be released + */ + cpu_release = cpu; + __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); + flush_cache_all(); + /* + * Send a 'sev' to wake the secondary core again because + * ROM code will put core in WFE till the cpu_release + * flag is set. + */ + set_event(); + mb(); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (cpu_release == -1) + break; + + udelay(10); + } + + /* + * Now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return cpu_release != -1 ? -ENOSYS : 0; +} + +static void __init wakeup_secondary(void) +{ + + /* cpu is not to be released from the hold yet */ + cpu_release = -1; + + /* + * write the address of secondary startup into the system-wide + * AuxCoreBoot0 where ROM code will jump and start executing + * on secondary core + */ + __raw_writel(virt_to_phys(omap_secondary_startup), \ + OMAP4_AUXCOREBOOT_REG0); + /* + * Send a 'sev' to wake the secondary core from WFE. + */ + set_event(); + mb(); +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + unsigned int i, ncores = get_core_count(); + + for (i = 0; i < ncores; i++) + cpu_set(i, cpu_possible_map); +} + +void __init smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned int ncores = get_core_count(); + unsigned int cpu = smp_processor_id(); + int i; + + /* sanity check */ + if (ncores == 0) { + printk(KERN_ERR + "OMAP4: strange core count of 0? Default to 1\n"); + ncores = 1; + } + + if (ncores > num_possible_cpus()) { + printk(KERN_WARNING + "OMAP4: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, num_possible_cpus()); + ncores = num_possible_cpus(); + } + smp_store_cpu_info(cpu); + + /* + * are we trying to boot more cores than exist? + */ + if (max_cpus > ncores) + max_cpus = ncores; + +#ifdef CONFIG_LOCAL_TIMERS + /* + * Enable the local timer for primary CPU. If the device is + * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in + * omap_timer_init + */ + local_timer_setup(); +#endif + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + cpu_set(i, cpu_present_map); + + /* + * Initialise the SCU and wake up the secondary core using + * wakeup_secondary(). + */ + if (max_cpus > 1) { + scu_enable(); + /* + * Ensure that the data accessed by CPU0 before the SCU was + * initialised is visible to CPU1. + */ + flush_cache_all(); + wakeup_secondary(); + } +} diff --git a/arch/arm/plat-omap/include/mach/scu.h b/arch/arm/plat-omap/include/mach/scu.h new file mode 100644 index 0000000..2ee6660 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/scu.h @@ -0,0 +1,28 @@ +/* + * SCU regsiter header. + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Snoop Control Unit Registers. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __OMAP_ARCH_SCU_H +#define __OMAP_ARCH_SCU_H +/* + * SCU registers + */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c + +#endif diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h new file mode 100644 index 0000000..b6a3e67 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/smp.h @@ -0,0 +1,56 @@ +/* + * OMAP4 machine specific smp.h + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Interface functions needed for the SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2003 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_SMP_H +#define OMAP_ARCH_SMP_H + + +#include <asm/hardware/gic.h> + +/* + * set_event() is used to wake up secondary core from wfe using sev. ROM + * code puts the second core into wfe(standby). + * + */ + #define set_event() __asm__ __volatile__ ("sev" : : : "memory") + +/* + * We use Soft IRQ1 as the IPI + */ +static inline void smp_cross_call(cpumask_t callmap) +{ + gic_raise_softirq(callmap, 1); +} + +/* + * Can be useful for WFI boot strategy. + */ +static inline void smp_cross_call_done(cpumask_t callmap) +{ +} + +/* + * Read MPIDR: Multiprocessor affinity register + */ +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +#endif
This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430 SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> --- arch/arm/mach-omap2/omap-headsmp.S | 49 +++++++ arch/arm/mach-omap2/omap-smp.c | 238 +++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/mach/scu.h | 28 ++++ arch/arm/plat-omap/include/mach/smp.h | 56 ++++++++ 4 files changed, 371 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap2/omap-headsmp.S create mode 100644 arch/arm/mach-omap2/omap-smp.c create mode 100644 arch/arm/plat-omap/include/mach/scu.h create mode 100644 arch/arm/plat-omap/include/mach/smp.h