| Message ID | 1370281990-15090-4-git-send-email-mturquette@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
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Am Montag, 3. Juni 2013, 19:53:10 schrieb Mike Turquette: > Devicetree binding for the basic clock divider, plus the setup function > to register the clock. Based on the existing fixed-clock binding. > > Signed-off-by: Mike Turquette <mturquette@linaro.org> > --- [...] > +/** > + * of_div_clk_setup() - Setup function for simple div rate clock > + */ > +void of_divider_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + const char *clk_name = node->name; > + void __iomem *reg; > + const char *parent_name; > + u8 clk_divider_flags = 0; > + u8 mask = 0; > + u8 shift = 0; in the mux-clock these 3 are unsigned long and u32 types ... what is correct? > + struct clk_div_table *table; > + > + of_property_read_string(node, "clock-output-names", &clk_name); > + > + parent_name = of_clk_get_parent_name(node, 0); > + > + reg = of_iomap(node, 0); > + > + if (of_property_read_u8(node, "mask", &mask)) { > + pr_err("%s: missing mask property for %s\n", __func__, node->name); > + return; > + } > + > + if (of_property_read_u8(node, "shift", &shift)) > + pr_debug("%s: missing shift property defaults to zero for %s\n", > + __func__, node->name); same here ... mux reads u32 > + if (of_property_read_bool(node, "index_one")) > + clk_divider_flags |= CLK_DIVIDER_ONE_BASED; > + > + if (of_property_read_bool(node, "index_power_of_two")) > + clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO; > + > + if (of_property_read_bool(node, "index_allow_zero")) > + clk_divider_flags |= CLK_DIVIDER_ALLOW_ZERO; > + > + table = of_clk_get_div_table(node); > + if (IS_ERR(table)) > + return; > + > + clk = clk_register_divider_table(NULL, clk_name, > + parent_name, 0, > + reg, shift, mask, > + clk_divider_flags, table, > + NULL); this causes trouble, as the divider clock code above still requires a width instead of a mask. I remember talk about this going to change separately, but couldn't find anything of the sort in linux-next. > + > + if (!IS_ERR(clk)) > + of_clk_add_provider(node, of_clk_src_simple_get, clk); > +} > +EXPORT_SYMBOL_GPL(of_divider_clk_setup); > +CLK_OF_DECLARE(divider_clk, "divider-clock", of_divider_clk_setup); > +#endif
On 06/03/13 10:53, Mike Turquette wrote: > +Required properties: > +- compatible : shall be "divider-clock". > +- #clock-cells : from common clock binding; shall be set to 0. > +- clocks : link to phandle of parent clock > +- reg : base address for register controlling adjustable divider > +- mask : arbitrary bitmask for programming the adjustable divider > + > +Optional properties: > +- clock-output-names : From common clock binding. > +- table : array of integer pairs defining divisors & bitfield values > +- shift : number of bits to shift the mask, defaults to 0 if not present > +- index_one : valid divisor programming starts at 1, not zero > +- index_power_of_two : valid divisor programming must be a power of two > +- allow_zero : implies index_one, and programming zero results in > + divide-by-one It's preferred that property names have dashes instead of underscores.
On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd <sboyd@codeaurora.org> wrote: > On 06/03/13 10:53, Mike Turquette wrote: >> +Required properties: >> +- compatible : shall be "divider-clock". >> +- #clock-cells : from common clock binding; shall be set to 0. >> +- clocks : link to phandle of parent clock >> +- reg : base address for register controlling adjustable divider >> +- mask : arbitrary bitmask for programming the adjustable divider >> + >> +Optional properties: >> +- clock-output-names : From common clock binding. >> +- table : array of integer pairs defining divisors & bitfield values >> +- shift : number of bits to shift the mask, defaults to 0 if not present >> +- index_one : valid divisor programming starts at 1, not zero >> +- index_power_of_two : valid divisor programming must be a power of two >> +- allow_zero : implies index_one, and programming zero results in >> + divide-by-one > > It's preferred that property names have dashes instead of underscores. I think I have a suggestion or two here.. I mailed one to Mike earlier, I have had some mailing list problems which I think are solved now.. If you provide a mask for programming the divider, surely the "shift" property is therefore redundant. Unless some device has a completely strange way of doing things and uses two seperated bitfields for programming in the same register, the shift value is simply a function of ffs() on the mask, isn't it? It is nice to put the information specifically in the device tree, but where a shift is not specified it'd probably be a good idea to go about deriving that value that way anyway, right, and if we're doing that.. why specify it? Also it may be much simpler to simply define the default clock setup as being an integer divider that follows the form 2^n - I am not sure I can think off the top of my head of any clock dividers doing the rounds that have divide-by-non-power-of-two and if they exist out there (please correct me) they would be the rare ones. I think properties that modify behavior should err on the side of being rarely used and to define unusual behavior, not confirm the status quo. Just to be sure, though, someone would need to go visit a bunch of current clock handlers already implemented or read a lot of docs to see how they're expecting their dividers. Maybe some of the Samsung, Qualcomm, TI, Freescale guys can comment on what is the most common case inside their SoCs. In any case, once you figure out that, rather than specifying a full table of <0 1>, <1 2>, <2, 4> and creating a big list, you could just give the lower and upper limits and let the driver figure out what is in between with two values. If there were gaps, a full table would be necessary. The allow zero property might be better served by the very same range property. I would also say.. bit-mask rather than mask, divider-table rather than table, divider-range (modifying the idea above). While we're inside a particular namespace in the binding I think naming properties with their intent (i.e. what table is it?) is good behavior. -- Matt Sealey <matt@genesi-usa.com>
Quoting Matt Sealey (2013-06-04 10:39:53) > On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd <sboyd@codeaurora.org> wrote: > > On 06/03/13 10:53, Mike Turquette wrote: > >> +Required properties: > >> +- compatible : shall be "divider-clock". > >> +- #clock-cells : from common clock binding; shall be set to 0. > >> +- clocks : link to phandle of parent clock > >> +- reg : base address for register controlling adjustable divider > >> +- mask : arbitrary bitmask for programming the adjustable divider > >> + > >> +Optional properties: > >> +- clock-output-names : From common clock binding. > >> +- table : array of integer pairs defining divisors & bitfield values > >> +- shift : number of bits to shift the mask, defaults to 0 if not present > >> +- index_one : valid divisor programming starts at 1, not zero > >> +- index_power_of_two : valid divisor programming must be a power of two > >> +- allow_zero : implies index_one, and programming zero results in > >> + divide-by-one > > > > It's preferred that property names have dashes instead of underscores. > > I think I have a suggestion or two here.. > > I mailed one to Mike earlier, I have had some mailing list problems > which I think are solved now.. > > If you provide a mask for programming the divider, surely the "shift" > property is therefore redundant. Unless some device has a completely > strange way of doing things and uses two seperated bitfields for > programming in the same register, the shift value is simply a function > of ffs() on the mask, isn't it? It is nice to put the information > specifically in the device tree, but where a shift is not specified > it'd probably be a good idea to go about deriving that value that way > anyway, right, and if we're doing that.. why specify it? > Shift is optional. Also I think the integer values in a DTS are 32-bits, so if some day someone had a clock driver that needed to write to a 64-bit register then shift might be useful there, combined with a 32-bit mask. Or perhaps dtc will have a 64-bit value for that case? I don't know. I certainly do see your point about only using the mask, and the original clock basic types did this a while back before the shift+width style came into vogue. If other reviewers also want to use a pure 32-bit mask and no shift then I'll drop it in the next round. > Also it may be much simpler to simply define the default clock setup > as being an integer divider that follows the form 2^n - I am not sure > I can think off the top of my head of any clock dividers doing the > rounds that have divide-by-non-power-of-two and if they exist out > there (please correct me) they would be the rare ones. I think > properties that modify behavior should err on the side of being rarely > used and to define unusual behavior, not confirm the status quo. > Please review the current use of CLK_DIVIDER_POWER_OF_TWO in the kernel. The only platform using this flag for power-of-two dividers is OMAP2430. Based on usage of clk_register_divider I think the common case is a clock divider that divides by any integer value programmed into it, up to the limit of the bitfield width. Perhaps your platform is the corner case, in which case power-of-two is the property you should use. > Just to be sure, though, someone would need to go visit a bunch of > current clock handlers already implemented or read a lot of docs to > see how they're expecting their dividers. Maybe some of the Samsung, > Qualcomm, TI, Freescale guys can comment on what is the most common > case inside their SoCs. > The following platforms use the basic divider without the power-of-two flag: imx6, loongson1B, mmp2, pxa168, pxa190, spearX, sunxi, tegra2/3/114, omap2+. > In any case, once you figure out that, rather than specifying a full > table of <0 1>, <1 2>, <2, 4> and creating a big list, you could just > give the lower and upper limits and let the driver figure out what is > in between with two values. If there were gaps, a full table would be > necessary. The allow zero property might be better served by the very > same range property. > You have described how it already works. The table is only there for when a common formula fails to capture the possible divisor combinations. For the default the driver starts the index at 0 and goes up to mask/width, for index_one the driver does the same but starts at 1, not 0, for power of two ... well you get the picture. The table is only of use when these common divider schemes are insufficient to determine the divisors. > I would also say.. bit-mask rather than mask, divider-table rather > than table, divider-range (modifying the idea above). While we're > inside a particular namespace in the binding I think naming properties > with their intent (i.e. what table is it?) is good behavior. > I'll make the properties more verbose in the next patch. Thanks for the review, Mike > -- > Matt Sealey <matt@genesi-usa.com>
On Tue, Jun 4, 2013 at 2:22 PM, Mike Turquette <mturquette@linaro.org> wrote: > Quoting Matt Sealey (2013-06-04 10:39:53) >> On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd <sboyd@codeaurora.org> wrote: >> > On 06/03/13 10:53, Mike Turquette wrote: >> >> +Required properties: >> >> +- compatible : shall be "divider-clock". >> >> +- #clock-cells : from common clock binding; shall be set to 0. >> >> +- clocks : link to phandle of parent clock >> >> +- reg : base address for register controlling adjustable divider >> >> +- mask : arbitrary bitmask for programming the adjustable divider >> >> + >> >> +Optional properties: >> >> +- clock-output-names : From common clock binding. >> >> +- table : array of integer pairs defining divisors & bitfield values >> >> +- shift : number of bits to shift the mask, defaults to 0 if not present >> >> +- index_one : valid divisor programming starts at 1, not zero >> >> +- index_power_of_two : valid divisor programming must be a power of two >> >> +- allow_zero : implies index_one, and programming zero results in >> >> + divide-by-one >> > >> > It's preferred that property names have dashes instead of underscores. >> >> I think I have a suggestion or two here.. >> >> I mailed one to Mike earlier, I have had some mailing list problems >> which I think are solved now.. >> >> If you provide a mask for programming the divider, surely the "shift" >> property is therefore redundant. Unless some device has a completely >> strange way of doing things and uses two seperated bitfields for >> programming in the same register, the shift value is simply a function >> of ffs() on the mask, isn't it? It is nice to put the information >> specifically in the device tree, but where a shift is not specified >> it'd probably be a good idea to go about deriving that value that way >> anyway, right, and if we're doing that.. why specify it? > > Shift is optional. Also I think the integer values in a DTS are > 32-bits, so if some day someone had a clock driver that needed to write > to a 64-bit register then shift might be useful there, combined with a > 32-bit mask. Or perhaps dtc will have a 64-bit value for that case? I > don't know. > > I certainly do see your point about only using the mask, and the > original clock basic types did this a while back before the shift+width > style came into vogue. > > If other reviewers also want to use a pure 32-bit mask and no shift then > I'll drop it in the next round. Hmm.. that's a very good point... You can't have a 64-bit OF property unless you're on a 64-bit platform or do some really weird workarounds for it (multiple cells etc.). That's how the OF spec was laid out, it sucks.. but it's the standard and the DT seems to stay compatible with the general concept. A supplemental binding to support clock dividers living in 64-bit registers may be a better way. You'd need a shift for the mask if you could only do a 32-bit property (32-bit platform with a 4-byte cell size) and a shift for the bits that would go into the mask as well as a width property for the register size to bound the shift.. Too complicated for now. I would say stick with 32-bit until this magical 64-bit divider register appears, and then do something slightly different :) >> Also it may be much simpler to simply define the default clock setup >> as being an integer divider that follows the form 2^n - I am not sure >> I can think off the top of my head of any clock dividers doing the >> rounds that have divide-by-non-power-of-two and if they exist out >> there (please correct me) they would be the rare ones. I think >> properties that modify behavior should err on the side of being rarely >> used and to define unusual behavior, not confirm the status quo. > > Please review the current use of CLK_DIVIDER_POWER_OF_TWO in the kernel. You're right, I think I got it backwards or was actually thinking of allow_zero (as in, 0x0 divider = divide by 1)? i.MX definitely has more 0x0=div-by-1 than any other kind.. >> In any case, once you figure out that, rather than specifying a full >> table of <0 1>, <1 2>, <2, 4> and creating a big list, you could just >> give the lower and upper limits and let the driver figure out what is >> in between with two values. If there were gaps, a full table would be >> necessary. The allow zero property might be better served by the very >> same range property. > > You have described how it already works. The table is only there for > when a common formula fails to capture the possible divisor > combinations. For the default the driver starts the index at 0 and goes > up to mask/width, for index_one the driver does the same but starts at > 1, not 0, for power of two ... well you get the picture. The table is > only of use when these common divider schemes are insufficient to > determine the divisors. Right, but in the case of index_one and allow_zero, one property for ranges basically covers the case where a slight modification to the formula used would be required, and allows specifying the first valid divider and the last valid divider which might come in handy when you have a mask of a certain size (say, 6 bits), but the actual divider is only 4 bits wide. You may need to ensure that you clear reserved bits within that masked region, but not use the mask itself to calculate the full range. I can't think of a good case but on i.MX53 the DVFSP load tracking register 1 has a field that subdivides the ARM core clock by 1, 2 or 3 (using 0, 1 or 2 as the divider value) in a 6-bit field, where 000011-111111 are reserved. I would think the correct value for the mask is the full 6-bit field, but the range should define that only 1-3 are valid (saving one entry). It isn't really something that would end up using a clock framework divider though. If there's a divider built for future expandability or somehow restricted at the design level to only accept a few bits, or only 'restricted' at the documentation level (.. it's been done) then it might be best to use the mask to mask off the register, and not to define valid bits to set, unless you resolve to specify two masks.. but a range property would be better and cover every case, while not having to force DT writers to list every divider in a big field (imagine if it's 3 bits that's a 16 entry table.. there are some 5 and 6-bit clock dividers floating around), I think an opportunity to consolidate two properties into one AND give an easy out to oddly-ranged dividers (where low and high divider settings may be 'invalid' but between those values is a contiguous range of a significant number of values (and here I would say, more than 2). Since we shouldn't be guessing, divider-p-o-2 is still required but as you corrected me.. rarer. >> I would also say.. bit-mask rather than mask, divider-table rather >> than table, divider-range (modifying the idea above). While we're >> inside a particular namespace in the binding I think naming properties >> with their intent (i.e. what table is it?) is good behavior. >> > > I'll make the properties more verbose in the next patch. Lovely :)
Am Dienstag, 4. Juni 2013, 21:22:43 schrieb Mike Turquette: > Quoting Matt Sealey (2013-06-04 10:39:53) > > > On Tue, Jun 4, 2013 at 12:11 PM, Stephen Boyd <sboyd@codeaurora.org> wrote: > > > On 06/03/13 10:53, Mike Turquette wrote: > > >> +Required properties: > > >> +- compatible : shall be "divider-clock". > > >> +- #clock-cells : from common clock binding; shall be set to 0. > > >> +- clocks : link to phandle of parent clock > > >> +- reg : base address for register controlling adjustable divider > > >> +- mask : arbitrary bitmask for programming the adjustable divider > > >> + > > >> +Optional properties: > > >> +- clock-output-names : From common clock binding. > > >> +- table : array of integer pairs defining divisors & bitfield values > > >> +- shift : number of bits to shift the mask, defaults to 0 if not > > >> present +- index_one : valid divisor programming starts at 1, not > > >> zero +- index_power_of_two : valid divisor programming must be a > > >> power of two +- allow_zero : implies index_one, and programming zero > > >> results in + divide-by-one > > > > > > It's preferred that property names have dashes instead of underscores. > > > > I think I have a suggestion or two here.. > > > > I mailed one to Mike earlier, I have had some mailing list problems > > which I think are solved now.. > > > > If you provide a mask for programming the divider, surely the "shift" > > property is therefore redundant. Unless some device has a completely > > strange way of doing things and uses two seperated bitfields for > > programming in the same register, the shift value is simply a function > > of ffs() on the mask, isn't it? It is nice to put the information > > specifically in the device tree, but where a shift is not specified > > it'd probably be a good idea to go about deriving that value that way > > anyway, right, and if we're doing that.. why specify it? > > Shift is optional. Also I think the integer values in a DTS are > 32-bits, so if some day someone had a clock driver that needed to write > to a 64-bit register then shift might be useful there, combined with a > 32-bit mask. Or perhaps dtc will have a 64-bit value for that case? I > don't know. > > I certainly do see your point about only using the mask, and the > original clock basic types did this a while back before the shift+width > style came into vogue. > > If other reviewers also want to use a pure 32-bit mask and no shift then > I'll drop it in the next round. I would object to dropping the shift :-) If you look at the two clk extensions in my rockchip patches you can see that they use a different regiment to set values. Using the lower 16 bits to set the value and the upper 16 bit to mark which values are changed, i.e. (mask << shift + 16) | (val << shift). (I'm not sure, if the naming or solution could be improved though) Heiko
Quoting Heiko Stübner (2013-06-03 15:18:32) > Am Montag, 3. Juni 2013, 19:53:10 schrieb Mike Turquette: > > Devicetree binding for the basic clock divider, plus the setup function > > to register the clock. Based on the existing fixed-clock binding. > > > > Signed-off-by: Mike Turquette <mturquette@linaro.org> > > --- > > [...] > > > +/** > > + * of_div_clk_setup() - Setup function for simple div rate clock > > + */ > > +void of_divider_clk_setup(struct device_node *node) > > +{ > > + struct clk *clk; > > + const char *clk_name = node->name; > > + void __iomem *reg; > > + const char *parent_name; > > + u8 clk_divider_flags = 0; > > + u8 mask = 0; > > + u8 shift = 0; > > in the mux-clock these 3 are unsigned long and u32 types ... what is correct? > Good catch. Shifts should be u8, masks should be u32. I've left the flags as u8. The binding doesn't dictate this and if we end up having more flags (hopefully not!) then this value can be embiggened. > > > + struct clk_div_table *table; > > + > > + of_property_read_string(node, "clock-output-names", &clk_name); > > + > > + parent_name = of_clk_get_parent_name(node, 0); > > + > > + reg = of_iomap(node, 0); > > + > > + if (of_property_read_u8(node, "mask", &mask)) { > > + pr_err("%s: missing mask property for %s\n", __func__, node->name); > > + return; > > + } > > + > > + if (of_property_read_u8(node, "shift", &shift)) > > + pr_debug("%s: missing shift property defaults to zero for %s\n", > > + __func__, node->name); > > same here ... mux reads u32 > > > + if (of_property_read_bool(node, "index_one")) > > + clk_divider_flags |= CLK_DIVIDER_ONE_BASED; > > + > > + if (of_property_read_bool(node, "index_power_of_two")) > > + clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO; > > + > > + if (of_property_read_bool(node, "index_allow_zero")) > > + clk_divider_flags |= CLK_DIVIDER_ALLOW_ZERO; > > + > > + table = of_clk_get_div_table(node); > > + if (IS_ERR(table)) > > + return; > > + > > + clk = clk_register_divider_table(NULL, clk_name, > > + parent_name, 0, > > + reg, shift, mask, > > + clk_divider_flags, table, > > + NULL); > > this causes trouble, as the divider clock code above still requires a width > instead of a mask. I remember talk about this going to change separately, but > couldn't find anything of the sort in linux-next. Right. I viewed creation of the DT bindings a bit separately from the CCF code, which I think is the right approach. A mask is definitely a more useful structure than a width value, and the DT bindings need to be at least a little future-proof, so I chose a mask. I'll update the divider code to use a mask and post that as part of the v2 series. Regards, Mike > > > > > + > > + if (!IS_ERR(clk)) > > + of_clk_add_provider(node, of_clk_src_simple_get, clk); > > +} > > +EXPORT_SYMBOL_GPL(of_divider_clk_setup); > > +CLK_OF_DECLARE(divider_clk, "divider-clock", of_divider_clk_setup); > > +#endif
diff --git a/Documentation/devicetree/bindings/clock/divider-clock.txt b/Documentation/devicetree/bindings/clock/divider-clock.txt new file mode 100644 index 0000000..31e9273 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/divider-clock.txt @@ -0,0 +1,80 @@ +Binding for simple divider clock. + +This binding uses the common clock binding[1]. It assumes a +register-mapped adjustable clock rate divider that does not gate and has +only one input clock or parent. By default the value programmed into +the register is one less than the actual divisor value. E.g: + +register value actual divisor value +0 1 +1 2 +2 3 + +This assumption may be modified by the following optional properties: + +index_one - valid divisor values start at 1, not the default of 0. E.g: +register value actual divisor value +1 1 +2 2 +3 3 + +index_power_of_two - valid divisor values are powers of two. E.g: +register value actual divisor value +0 1 +1 2 +2 4 + +allow_zero - same as index_one, but zero is divide-by-1. E.g: +register value actual divisor value +0 1 +1 1 +2 2 + +Additionally a table of valid dividers may be supplied like so: + + table = <4 0>, <8, 1>; + +where the first value in the pair is the divider and the second value is +the programmed register bitfield. + +The binding must also provide the register to control the divider and +the mask for the corresponding control bits. Optionally the number of +bits to shift that mask, if necessary. If the shift value is missing it +is the same as supplying a zero shift. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "divider-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link to phandle of parent clock +- reg : base address for register controlling adjustable divider +- mask : arbitrary bitmask for programming the adjustable divider + +Optional properties: +- clock-output-names : From common clock binding. +- table : array of integer pairs defining divisors & bitfield values +- shift : number of bits to shift the mask, defaults to 0 if not present +- index_one : valid divisor programming starts at 1, not zero +- index_power_of_two : valid divisor programming must be a power of two +- allow_zero : implies index_one, and programming zero results in + divide-by-one + +Examples: + clock_foo: clock_foo@4a008100 { + compatible = "divider-clock"; + #clock-cells = <0>; + clocks = <&clock_baz>; + reg = <0x4a008100 0x4> + mask = <0x3> + }; + + clock_bar: clock_bar@4a008108 { + #clock-cells = <0>; + compatible = "divider-clock"; + clocks = <&clock_foo>; + reg = <0x4a008108 0x4>; + mask = <0x1>; + shift = <0>; + table = < 4 0 >, < 8 1 >; + }; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6d96741..3b76591 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> - * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> + * Copyright (C) 2011-2013 Mike Turquette, Linaro Ltd <mturquette@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -17,6 +17,8 @@ #include <linux/err.h> #include <linux/string.h> #include <linux/log2.h> +#include <linux/of.h> +#include <linux/of_address.h> /* * DOC: basic adjustable divider clock that cannot gate @@ -320,3 +322,87 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, return _register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, table, lock); } + +#ifdef CONFIG_OF +struct clk_div_table *of_clk_get_div_table(struct device_node *node) +{ + int i; + int table_size = 0; + struct clk_div_table *table; + u32 pair[2]; + + table_size = of_count_phandle_with_args(node, "table", "#clock-cells"); + + if (table_size < 1) + return NULL; + + table = kzalloc(sizeof(struct clk_div_table) * table_size, GFP_KERNEL); + if (!table) { + pr_err("%s: unable to allocate memory for %s table\n", __func__, node->name); + return NULL; + } + + for (i = 0; i < table_size; i++) { + if (!of_property_read_u32_array(node, "table", pair, ARRAY_SIZE(pair))) { + table[i].val = pair[0]; + table[i].div = pair[1]; + } + } + + return table; +} + +/** + * of_div_clk_setup() - Setup function for simple div rate clock + */ +void of_divider_clk_setup(struct device_node *node) +{ + struct clk *clk; + const char *clk_name = node->name; + void __iomem *reg; + const char *parent_name; + u8 clk_divider_flags = 0; + u8 mask = 0; + u8 shift = 0; + struct clk_div_table *table; + + of_property_read_string(node, "clock-output-names", &clk_name); + + parent_name = of_clk_get_parent_name(node, 0); + + reg = of_iomap(node, 0); + + if (of_property_read_u8(node, "mask", &mask)) { + pr_err("%s: missing mask property for %s\n", __func__, node->name); + return; + } + + if (of_property_read_u8(node, "shift", &shift)) + pr_debug("%s: missing shift property defaults to zero for %s\n", + __func__, node->name); + + if (of_property_read_bool(node, "index_one")) + clk_divider_flags |= CLK_DIVIDER_ONE_BASED; + + if (of_property_read_bool(node, "index_power_of_two")) + clk_divider_flags |= CLK_DIVIDER_POWER_OF_TWO; + + if (of_property_read_bool(node, "index_allow_zero")) + clk_divider_flags |= CLK_DIVIDER_ALLOW_ZERO; + + table = of_clk_get_div_table(node); + if (IS_ERR(table)) + return; + + clk = clk_register_divider_table(NULL, clk_name, + parent_name, 0, + reg, shift, mask, + clk_divider_flags, table, + NULL); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +EXPORT_SYMBOL_GPL(of_divider_clk_setup); +CLK_OF_DECLARE(divider_clk, "divider-clock", of_divider_clk_setup); +#endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9c404c2..63521e7 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -283,6 +283,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); +void of_divider_clk_setup(struct device_node *node); + /** * struct clk_mux - multiplexer clock *
Devicetree binding for the basic clock divider, plus the setup function to register the clock. Based on the existing fixed-clock binding. Signed-off-by: Mike Turquette <mturquette@linaro.org> --- .../devicetree/bindings/clock/divider-clock.txt | 80 ++++++++++++++++++++ drivers/clk/clk-divider.c | 88 +++++++++++++++++++++- include/linux/clk-provider.h | 2 + 3 files changed, 169 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/divider-clock.txt