diff mbox

[5/5] ARM: KVM: issue a DSB after cache maintainance operations

Message ID 1371648006-8036-6-git-send-email-marc.zyngier@arm.com (mailing list archive)
State New, archived
Headers show

Commit Message

Marc Zyngier June 19, 2013, 1:20 p.m. UTC 
When performing the Set/Way cache maintainance operations, it is
important to make sure the operation completes by issueing a DSB.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/kvm/coproc.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Will Deacon June 20, 2013, 10:46 a.m. UTC | #1 
On Wed, Jun 19, 2013 at 02:20:06PM +0100, Marc Zyngier wrote:
> When performing the Set/Way cache maintainance operations, it is
> important to make sure the operation completes by issueing a DSB.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm/kvm/coproc.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
> index 4a51990..9e6bef4 100644
> --- a/arch/arm/kvm/coproc.c
> +++ b/arch/arm/kvm/coproc.c
> @@ -106,6 +106,8 @@ static bool access_dcsw(struct kvm_vcpu *vcpu,
>  		break;
>  	}
>  
> +	dsb();

Worth noting that this can become -ishst once my barriers branch goes
upstream (aiming for 3.12).

Will
diff mbox

Patch

diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 4a51990..9e6bef4 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -106,6 +106,8 @@  static bool access_dcsw(struct kvm_vcpu *vcpu,
 		break;
 	}
 
+	dsb();
+
 done:
 	put_cpu();